Modeling magnetic coupling for on-chip interconnect

ABSTRACT

As advances in IC technologies and operat-ing frequencies make the modeling of on-chip magnetic interactions a necessity, it is apparent that extension of traditional inductance extraction approaches to full-chip scale problems is impractical. There are primarily two obstacles to performing inductance extraction with the same efficacy as full-chip capacitance extraction: 1) ne-glecting far-away coupling terms can generate an unsta-ble inductance matrix approximation; and 2) the penetrating nature of inductance makes localized extrac-tion via windowing extremely difficult. In this paper we propose and contrast three new options for stable and ac-curate window-based extraction of large-scale magnetic coupling. We analyze the required window sizes to con-sider the possibilities for pattern-matching style solu-tions, and propose three schemes for determining coupling values and window sizing for extraction via on-the-fly field solution.

REFERENCES

• 1: Michael W. Beattie , Lawrence T. Pileggi, IC analyses including extracted inductance models, Proceedings of the 36th ACM/IEEE conference on Design automation, p.915-920, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310098]
• 2: L. Nagel, R. Rohrer, Computer Analysis of Nonlinear circuits, Excluding Radiation (CANCER), IEEE J. Solid State Circ., SC-6, pp. 162-182 (Aug. 1971).
• 3: M. Beattle , L. Pileggi, Efficient inductance extraction via windowing, Proceedings of the conference on Design, automation and test in Europe, p.430-436, March 2001, Munich, Germany
• 4: Mariusz Niewczas , Wojciech Maly , Andrzej Strojwas, A pattern matching algorithm for verification and analysis of very large IC layouts, Proceedings of the 1998 international symposium on Physical design, p.129-134, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274554]
• 5: J. Jackson, Classical Electrodynamics, 2 nd Ed., John Wiley & Sons, New York (1975).
• 6: Anirudh Devgan , Hao Ji , Wayne Dai, How to efficiently capture on-chip inductance effects: introducing a new circuit element K, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 7: D. Ling, A. Ruehli, Interconnection Modeling, in: Circuit Analysis, Simulation and Design, Elsevier Science Publishers B.V., North-Holland, (1987).
• 8: I. N. Bronshtein , K. A. Semendyayev , K. A. Kirsch, Handbook of mathematics (3rd ed.), Springer-Verlag, London, 1997
• 9: Gene H. Golub , Charles F. Van Loan, Matrix computations (3rd ed.), Johns Hopkins University Press, Baltimore, MD, 1996
• 10: William H. Press , Saul A. Teukolsky , William T. Vetterling , Brian P. Flannery, Numerical recipes in C (2nd ed.): the art of scientific computing, Cambridge University Press, New York, NY, 1992
• 11: Roger A. Horn , Charles R. Johnson, Matrix analysis, Cambridge University Press, New York, NY, 1985
• 12: E. Rosa, The Self and Mutual Inductance of Linear Conductors, Bulletin of the National Bureau of Standards, 4, pp. 301-344 (1908).
• 13: Byron Krauter , Lawrence T. Pileggi, Generating sparse partial inductance matrices with guaranteed stability, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.45-52, November 05-09, 1995, San Jose, California, United States
• 14: M. Beattie, L. Alatan, L. Pileggi, Equipotential Shells for Efficient Partial Inductance Extraction, Proc. 1998 IEDM (December 1998).

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory

Keywords:
inductance, interconnect modeling, magnetic interaction, susceptance