Inductance 101

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Inductance 101: modeling and extraction

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 323 - 328

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

Michael W. Beattie	Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania, 15213
Lawrence T. Pileggi	Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania, 15213

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 12

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for inte-grated circuit design in recent years. This tutorial paper de-scribes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency ef-fects such as skin and proximity effect.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kaushik Gala , David Blaauw , Junfeng Wang , Vladimir Zolotov , Min Zhao, Inductance 101: analysis and design issues, Proceedings of the 38th conference on Design automation, p.329-334, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378501]
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	11	M. Kamon, M. Tsuk, J. White, FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction Program, IEEE Trans. Microwave Theory and Techniques, 42, No. 9, pg. 1750-1758 (Sept. 1994).
	12	J. Wang , J. Tausch , J. White, A wide frequency range surface integral formulation for 3-D RLC extraction, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.453-458, November 07-11, 1999, San Jose, California, United States
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	14	S. Morton, Techniques for driving interconnect, in Design of High-Performance Microprocessor Circuits, Ed. A. Chandrakasan, et al., pp. 352-376, IEEE Press (2001).

CITED BY 12

	Clement Luk , Tsung-Hao Chen , Charlie C.-P. Chen, Frequency-dependent reluctance extraction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.792-797, January 27-30, 2004, Yokohama, Japan
	Rafael Escovar , Salvador Ortiz , Roberto Suaya, Mutual inductance extraction and the dipole approximation, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Shang-Wei Tu , Wen-Zen Shen , Yao-Wen Chang , Tai-Chen Chen , Jing-Yang Jou, Inductance Modeling for On-Chip Interconnects, Analog Integrated Circuits and Signal Processing, v.35 n.1, p.65-78, April 2003
	Satrajit Gupta , Lawrence T. Pileggi, CHIME: coupled hierarchical inductance model evaluation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Takashi Sato , Hiroo Masuda, Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay, Analog Integrated Circuits and Signal Processing, v.42 n.3, p.209-217, March 2005
	Tsung-Hao Chen , Clement Luk , Hyungsuk Kim , Charlie Chung-Ping Chen, INDUCTWISE: inductance-wise interconnect simulator and extractor, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.215-220, November 10-14, 2002, San Jose, California
	Mengsheng Zhang , Wenjian Yu , Yu Du , Zeyi Wang, An efficient algorithm for 3-D reluctance extraction considering high frequency effect, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Yehia Massoud , Arthur Nieuwoudt, Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.2 n.3, p.155-196, July 2006
	Hoyeol Cho , Kyung-Hoae Koo , Pawan Kapur , Krishna C. Saraswat, Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Dimitrios Velenis , Marios C. Papaefthymiou , Eby G. Friedman, Reduced Delay Uncertainty in High Performance Clock Distribution Networks, Proceedings of the conference on Design, Automation and Test in Europe, p.10068, March 03-07, 2003
	Rong Jiang , Charlie Chung-Ping Chen, SCORE: SPICE COmpatible Reluctance Extraction, Proceedings of the conference on Design, automation and test in Europe, p.20948, February 16-20, 2004
	Mosin Mondal , Yehia Massoud, Accurate loop self inductance bound for efficient inductance screening, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.12, p.1393-1397, December 2006