Static timing analysis including power supply noise effect on propagation delay in VLSI circuits

ABSTRACT

This paper presents techniques to include the effect of supply voltage noise on the circuit propagation delay of a digital VLSI circuit. The proposed methods rely on an input-independent approach to calculate the logic gate's worst-case power supply noise. A quasi-static timing analysis is then applied to derive a tight upper-bound on the delay for a selected path with power supply noise effects. This upper-bound can be further reduced by considering the logic constraints and dependencies in the circuit. Experimental results for ISCAS-85 benchmark circuits are presented using the techniques described in the paper. HSPICE simulation results are also used to validate our work.

REFERENCES

• 1: G.Bai and I.N.Hajj. Maximum power supply noise estimation in VLSI circuits via a pareto genetic algorithms. Submitted to International Symposium on Low Power Electronics and Design, August 2001.
• 2: G. Bai , S. Bobba , I. N. Hajj, Power Bus Maximum Voltage Drop in Digital VLSI Circuits, Proceedings of the 1st International Symposium on Quality of Electronic Design, p.263, March 20-22, 2000
• 3: G.Bai, S.Bobba, and I.N.Hajj. Maximum power supply noise estimation in digital VLSI circuits using multimodal genetic algorithms. Submitted to International Conference on Electronics Circuits and Systems, September 2001.
• 4: RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits, Proceedings of the 2nd International Symposium on Quality Electronic Design, p.257, March 26-28, 2001
• 5: D. H. Du , S. H. Yen , S. Ghanta, On the general false path problem in timing analysis, Proceedings of the 26th ACM/IEEE conference on Design automation, p.555-560, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74475]
• 6: H. C. Yen , S. Ghanta , H. C. Du, A path selection algorithm for timing analysis, Proceedings of the 25th ACM/IEEE conference on Design automation, p.720-723, June 12-15, 1988, Atlantic City, New Jersey, United States
• 7: H.Kriplani, F.N.Najm, and I.N.Hajj. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 14(8):998-1012, August 1995.
• 8: Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
• 9: S.Bobba and I.N.Hajj. Estimation of maximum switching activity in digital VLSI circuits. In Proceedings of Midwest Symposium on Circuits and System, pages 1130-1133, August 1997.
• 10: S. Bobba , I. N. Hajj, Estimation of maximum current envelope for power bus analysis and design, Proceedings of the 1998 international symposium on Physical design, p.141-146, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274556]
• 11: Yi-Min Jiang , Angela Krstic , Kwang-Ting (Tim) Cheng, Dynamic Timing Analysis Considering Power Supply Noise Effects, Proceedings of the 1st International Symposium on Quality of Electronic Design, p.137, March 20-22, 2000
• 12: Yi-Min Jiang , Kwang-Ting Cheng, Analysis of performance impact caused by power supply noise in deep submicron devices, Proceedings of the 36th ACM/IEEE conference on Design automation, p.760-765, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310053]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation
  B.8 Performance and Reliability

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.2 Installation Management
          Subjects: Benchmarks

General Terms:
Design, Experimentation, Measurement, Performance, Standardization, Theory