Parallelizing DSP nested loops on reconfigurable architectures using data context switching

ABSTRACT

Reconfigurable architectures promise significant performance and flexibility advantages over conventional architectures. Automatic mapping techniques that exploit the features of the hardware are needed to leverage the power of these architectures. In this paper, we develop techniques for parallelizing nested loop computations from digital signal processing (DSP) applications onto high performance pipelined configurations. We propose a novel data context switching technique that exploits the embedded distributed memory available in reconfigurable architectures to parallelize such loops. Our technique is demonstrated on two diverse state-of-the-art reconfigurable architectures, namely, Virtex and the Chameleon Systems Reconfigurable Communications Processor. Our techniques show significant performance improvements on both architectures and also perform better than state-of-the-art DSP and microprocessor architectures.

REFERENCES

• 1: Kiran Bondalapati , Viktor K. Prasanna, Mapping Loops onto Reconfigurable Architectures, Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, p.268-277, August 31-September 03, 1998
• 2: Kiran Bondalapati , Viktor K. Prasanna, Loop Pipelining and Optimization for Run Time Reconfiguration, Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing, p.906-915, May 01-05, 2000
• 3: Bill Salefski , Levent Caglar, Re-configurable computing in wireless, Proceedings of the 38th conference on Design automation, p.178-183, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378459]
• 4: Chameleon Systems. http://www.chameleonsystems.com/.
• 5: Xilinx Inc.(www.xilinx.com). Virtex Series FPGAs.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

Additional Classification:
  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory

Keywords:
configurable computing, loops, mapping techniques