Validating the intel pentium 4 microprocessor

ABSTRACT

Developing a new leading edge IA-32 micro-processor is an immensely complicated undertaking. In the case of the Pentium© 4 processor, the microarchitecture is significantly more complex than any previous IA-32 microprocessor and the implementation borrows almost nothing from any previous implementation. This paper describes how we went about the task of finding bugs in the Pentium© 4 processor design prior to initial silicon, and what we found along the way.

REFERENCES

• 1: Laurent Fournier , Yaron Arbetman , Moshe Levinger, Functional verification methodology for microprocessors using the Genesys test-program generator, Proceedings of the conference on Design, automation and test in Europe, p.92-es, January 1999, Munich, Germany [doi>10.1145/307418.307540]
• 2: Richard C. Ho , C. Han Yang , Mark A. Horowitz , David L. Dill, Architecture validation for processors, Proceedings of the 22nd annual international symposium on Computer architecture, p.404-413, June 22-24, 1995, S. Margherita Ligure, Italy
• 3: Zucker, R, "Bug Root Cause Analysis for Willamette", Intel Design and Test Technology Conference, August 2000.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers

          Nouns: Intel Pentium

Additional Classification:
  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Management, Measurement, Performance, Theory, Verification