Re-configurable computing in wireless

ABSTRACT

Wireless communications requires a new approach to implement the algorithms for new standards. The computational demands of these standards are outstripping the ability of traditional signal processors, and standards are changing too quickly for traditional hardware implementation. In this paper we outline how reconfigurable processing can meet the needs for wireless base station design while providing the programmability to allow not just field upgrades as standards evolve, but also to adapt to much more dynamic factors in the environment such as traffic mix and the weather. We outline how a designer works with the Chameleon reconfigurable processor from algorithm design to prototyping on a development module.

REFERENCES

• 1: Rabey, Jan, Embedded Tutorial, ASPDAC00, Yokohama, January 2000
• 2: Horowitz, Mark. Circuits and Interconnect in Aggressively Scaled MOS, 37 th Design Automation Conference, Anaheim, California, June 2000
• 3: Kiran Bondalapati, Parallelizing DSP nested loops on reconfigurable architectures using data context switching, Proceedings of the 38th conference on Design automation, p.273-276, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378483]
• 4: http://brass.cs.berkeley.edu/SCORE/
• 5: http://www.ti.com/sc/docs/products/dsp/c6000/benchm arks/62x.htm

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design
          Subjects: Wireless communication

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Algorithms, Design, Performance, Theory