Test volume and application time reduction through scan chain concealment

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Test volume and application time reduction through scan chain concealment

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 151 - 155

Year of Publication: 2001

ISBN:1-58113-297-2

Authors

Ismet Bayraktaroglu	Computer Science & Engineering Department, University of California, San Diego, La Jolla, CA
Alex Orailoglu	Computer Science & Engineering Department, University of California, San Diego, La Jolla, CA

Sponsors

EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 15, Citation Count: 40

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ABSTRACT

A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of scan chains that can be supported by an ATE is significantly increased by utilizing an on-chip decompressor. The functionality of the ATE is kept intact by moving the decompression task to the circuit under test. While the number of virtual scan chains visible to the ATE is kept small, the number of internal scan chains driven by the decompressed pattern sequence can be sinificantly increased.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 40

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	Irith Pomeranz , Sudhakar M. Reddy, On test data compression and n-detection test sets, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Sudhakar M. Reddy , Kohei Miyase , Seiji Kajihara , Irith Pomeranz, On test data volume reduction for multiple scan chain designs, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.460-469, October 2003
	Wenjing Rao , Ismet Bayraktaroglu , Alex Orailoglu, Test application time and volume compression through seed overlapping, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Lei Li , Krishnendu Chakrabarty , Nur A. Touba, Test data compression using dictionaries with selective entries and fixed-length indices, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.8 n.4, p.470-490, October 2003
	Ismet Bayraktaroglu , Alex Orailoglu, Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs, IEEE Transactions on Computers, v.52 n.11, p.1480-1489, November 2003
	Janusz Rajski , Mark Kassab , Nilanjan Mukherjee , Nagesh Tamarapalli , Jerzy Tyszer , Jun Qian, Embedded Deterministic Test for Low-Cost Manufacturing, IEEE Design & Test, v.20 n.5, p.58-66, September 2003
	Paul Theo Gonciari , Bashir Al-Hashimi , Nicola Nicolici, Synchronization overhead in SOC compressed test, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.1, p.140-152, January 2005
	Abhijit Jas , Bahram Pouya , Nur A. Touba, Test data compression technique for embedded cores using virtual scan chains, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.775-780, July 2004
	C. V. Krishna , Abhijit Jas , Nur A. Touba, Achieving high encoding efficiency with partial dynamic LFSR reseeding, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.4, p.500-516, October 2004
	Anshuman Chandra , Krishnendu Chakrabarty, Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes, Journal of Electronic Testing: Theory and Applications, v.20 n.2, p.199-212, April 2004
	Xiaoyun Sun , Larry Kinney , Bapiraju Vinnakota, Combining dictionary coding and LFSR reseeding for test data compression, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Terumine Hayashi , Haruna Yoshioka , Tsuyoshi Shinogi , Hidehiko Kita , Haruhiko Takase, Test data compression technique using selective don't-care identification, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.230-233, January 27-30, 2004, Yokohama, Japan
	Lei Li , Krishnendu Chakrabarty, On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression, Journal of Electronic Testing: Theory and Applications, v.20 n.6, p.667-670, December 2004
	Ozgur Sinanoglu , Alex Orailoglu, Efficient Construction of Aliasing-Free Compaction Circuitry, IEEE Micro, v.22 n.5, p.82-92, September 2002
	Carl Barnhart , Vanessa Brunkhorst , Frank Distler , Owen Farnsworth , Andrew Ferko , Brion Keller , David Scott , Bernd Koenemann , Takeshi Onodera, Extending OPMISR beyond 10x Scan Test Efficiency, IEEE Design & Test, v.19 n.5, p.65-72, September 2002
	Ozgur Sinanoglu , Alex Orailoglu, Fast and energy-frugal deterministic test through efficient compression and compaction techniques, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.5, p.257-266, April 2004
	Mehrdad Nourani , Mohammad H. Tehranipour, RL-huffman encoding for test compression and power reduction in scan applications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.10 n.1, p.91-115, January 2005
	Youhua Shi , Nozomu Togawa , Shinji Kimura , Masao Yanagisawa , Tatsuo Ohtsuki, FCSCAN: an efficient multiscan-based test compression technique for test cost reduction, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Yasumi Doi , Seiji Kajihara , Xiaoqing Wen , Lei Li , Krishnendu Chakrabarty, Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Terumine Hayashi , Haruna Yoshioka , Tsuyoshi Shinogi , Hidehiko Kita , Haruhiko Takase, On test data compression using selective don't-care identification, Journal of Computer Science and Technology, v.20 n.2, p.210-215, March 2005
	Ozgur Sinanoglu, Low cost scan test by test correlation utilization, Journal of Computer Science and Technology, v.22 n.5, p.681-694, September 2007
	Grzegorz Mrugalski , Janusz Rajski , Jerzy Tyszer, Test response compactor with programmable selector, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Shih-Ping Lin , Chung-Len Lee , Jwu-E. Chen , Ji-Jan Chen , Kun-Lun Luo , Wen-Ching Wu, A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.7, p.767-776, July 2007
	Yinhe Han , Yu Hu , Xiaowei Li , Huawei Li , Anshuman Chandra, Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.5, p.531-540, May 2007
	Wenjing Rao , A. Orailoglu , G. Su, Frugal linear network-based test decompression for drastic test cost reductions, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.721-725, November 07-11, 2004
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	C. V. Krishna , Nur A. Touba, Adjustable Width Linear Combinational Scan Vector Decompression, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.863, November 09-13, 2003
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	Marie-Lise Flottes , Regis Poirier , Bruno Rouzeyre, An Arithmetic Structure for Test Data Horizontal Compression, Proceedings of the conference on Design, automation and test in Europe, p.10428, February 16-20, 2004
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