ACM Home Page
Please provide us with feedback. Feedback
Behavioral partitioning in the synthesis of mixed analog-digital systems
Full text PdfPdf (153 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 133 - 138  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
Sree Ganesan  Department of ECECS, ML 0030, University of Cincinnati, Cincinnati, OH
Ranga Vemuri  Department of ECECS, ML 0030, University of Cincinnati, Cincinnati, OH
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 11,   Citation Count: 3
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/378239.378373
What is a DOI?

ABSTRACT

Synthesis of mixed-signal designs from behavioral specifications must address analog-digital partitioning. In this paper, we investigate the issues in mixed-signal behavioral partitioning and design space exploration for signal-processing systems. We begin with the system behavior specified in an intermediate format called the Mixed Signal Flow Graph, based on the time-amplitude characterization of signals. We present techniques for analog-digital behavioral partitioning of the MSFG, and performance estimation of the technology-mapped analog and digital circuits. The partitioned solution must satisfy constrants on imposed by the target field programmable mixed-signal architecture on avaialable configurable resources, available data converters, their resolution and speed, and IO pins. The quality of the solution is evaluated based on two metrics, namely feasibility and performance. The former is a measure of the validity of the solution with respect to the architectural constraints. The latter measures the performance of the system based on bandwidth/speed and noise.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
2
 
3
S. Ganesan and R. Vemuri, "An FPGA/FPAA-Based Rapid Prototyping Environmentfor Mixed Signal Systems," in Reconfigurable Technology: FPGAs for Computing and Applications, Proc. of SPIE, vol. 3844, pp. 49-60, 1999.
 
4
S. Donnay et al., "High-level Analog/Digital Partitioning in Low-power Signal Processing Applications," in PATMOS, (Louvain-la-Neuve, Belgium), Sep. 1997.
 
5
 
6
 
7
A. Doboli and R. Vemuri, "aBlox - A Hierarchical Representation for Behavioral Synthesis of Analog Systems from VHDL-AMS," Tech. Rep. TR-DDEL, University of Cincinnati, April 1998.
 
8
J. Faura et al., "FIPSOC: A Field ProgrammableSystem On a Chip," in DCIS, 1997.
9
 
10
Inc. Zetex, TRAC User Guide, July 1997.
 
11
Inc. Motorola, Easy Analog Design Software User's Manual, October 1997. (Now Anadigm Inc., since 2000).
 
12
Inc. Xilinx, Xilinx Data Book, May 1999.
 
13
 
14
 
15
M. Nagata and A. Iwata, "Substrate Noise Simulation Techniques for Analog-Digital Mixed LSI Design," in IEICE Trans. Fundamentals, vol. E82-A, pp. 271-277, February 1999.


Collaborative Colleagues:
Sree Ganesan: colleagues
Ranga Vemuri: colleagues