| Reticle enhancement technology: implications and challenges for physical design |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 38th annual Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 73 - 78
Year of Publication: 2001
ISBN:1-58113-297-2
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Authors
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W. Grobman
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Motorola DigitalDNA Laboratories, Austin, TX
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M. Thompson
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Motorola DigitalDNA Laboratories, Austin, TX
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R. Wang
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Motorola DigitalDNA Laboratories, Austin, TX
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C. Yuan
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Motorola DigitalDNA Laboratories, Austin, TX
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R. Tian
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Motorola DigitalDNA Laboratories, Austin, TX
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E. Demircan
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Motorola DigitalDNA Laboratories, Austin, TX
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| Bibliometrics |
Downloads (6 Weeks): 17, Downloads (12 Months): 50, Citation Count: 4
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ABSTRACT
In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verificat ion. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Piotr Berman , Andrew B. Kahng , Devendra Vidhani , Huijuan Wang , Alex Zelikovsky, Optimal phase conflict removal for layout of dark field alternating phase shifting masks, Proceedings of the 1999 international symposium on Physical design, p.121-126, April 12-14, 1999, Monterey, California, United States
[doi> 10.1145/299996.300037]
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Yu Chen , Andrew B. Kahng , Gabriel Robins , Alexander Zelikovsky, Practical iterated fill synthesis for CMP uniformity, Proceedings of the 37th conference on Design automation, p.671-674, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337610]
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Kahng, A., Robins, G., Singh, A., and Zelikovsky, A. Filling Algorithms and Analyses for Layout Density Control. IEEE Trans. on CAD, 18(4):445-462, April 1999.
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Vikas Mehrotra , Shiou Lin Sam , Duane Boning , Anantha Chandrakasan , Rakesh Vallishayee , Sani Nassif, A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance, Proceedings of the 37th conference on Design automation, p.172-175, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337370]
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Tian, R., Wong, D.F., and Boone, R. Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability. IEEE Trans. on CAD, in press.
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Tian, R., Tang, X., and Wong, D. F. Tiling and Slotting for Process Uniformity Control in Copper Chemical-Mechanical Polishing. In Proc. 6 th CMP-MIC Conference (Santa Clara, California, March 2001), 57-62.
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Ruiqi Tian , Xiaoping Tang , D. F. Wong, Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process, Proceedings of the 2001 international symposium on Physical design, p.118-123, April 01-04, 2001, Sonoma, California, United States
[doi> 10.1145/369691.369750]
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Warren Grobman , Robert Boone , Cece Philbin , Bob Jarvis, Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs, Proceedings of the 2001 international symposium on Physical design, p.45-51, April 01-04, 2001, Sonoma, California, United States
[doi> 10.1145/369691.369730]
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Jackson, J. D. Classical Electrodynamics.
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Raphael User's Manual, AVANT, 1999.
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J.-K. Park, K.-H. Lee, Y.-K. Park, and J.-T. Kong, "An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing and Efficient Field Solving Algorithm," Simulation of Semiconductor Processes and Devices, 2000, pp. 98-10
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INDEX TERMS
Primary Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.1
Types and Design Styles
Subjects:
Advanced technologies
Additional Classification:
J.
Computer Applications
J.2
PHYSICAL SCIENCES AND ENGINEERING
Subjects:
Electronics
General Terms:
Design,
Measurement,
Performance,
Theory
Keywords:
OPC,
PSM,
RET,
mask data preparation,
optical proximity correction,
reticle enhancement technology,
subwavelength lithography,
tiling
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