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Reticle enhancement technology: implications and challenges for physical design
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 73 - 78  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
W. Grobman  Motorola DigitalDNA Laboratories, Austin, TX
M. Thompson  Motorola DigitalDNA Laboratories, Austin, TX
R. Wang  Motorola DigitalDNA Laboratories, Austin, TX
C. Yuan  Motorola DigitalDNA Laboratories, Austin, TX
R. Tian  Motorola DigitalDNA Laboratories, Austin, TX
E. Demircan  Motorola DigitalDNA Laboratories, Austin, TX
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 17,   Downloads (12 Months): 50,   Citation Count: 4
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ABSTRACT

In this paper, we review phase shift lithography, rule vs. model based methods for OPC and model-based tiling, and discuss their implications for layout and verificat ion. We will discuss novel approaches, using polarizing films on reticles, which change the game for phase-shift coloring, and could lead to a new direction in c:PSM constraints on physical design. We emphasize the need to do tiling that is model-driven and uses optimization techniques to achieve planarity for better manufacturing tolerance in the subwavelength dimensions era. Electromagnetic solver results will be presented which estimate the effect of tiling on circuit timing.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Kahng, A., Robins, G., Singh, A., and Zelikovsky, A. Filling Algorithms and Analyses for Layout Density Control. IEEE Trans. on CAD, 18(4):445-462, April 1999.
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Tian, R., Wong, D.F., and Boone, R. Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability. IEEE Trans. on CAD, in press.
 
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Tian, R., Tang, X., and Wong, D. F. Tiling and Slotting for Process Uniformity Control in Copper Chemical-Mechanical Polishing. In Proc. 6 th CMP-MIC Conference (Santa Clara, California, March 2001), 57-62.
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Jackson, J. D. Classical Electrodynamics.
 
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Raphael User's Manual, AVANT, 1999.
 
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J.-K. Park, K.-H. Lee, Y.-K. Park, and J.-T. Kong, "An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing and Efficient Field Solving Algorithm," Simulation of Semiconductor Processes and Devices, 2000, pp. 98-10


Collaborative Colleagues:
W. Grobman: colleagues
M. Thompson: colleagues
R. Wang: colleagues
C. Yuan: colleagues
R. Tian: colleagues
E. Demircan: colleagues