Instruction-level DFT for testing processor and IP cores in system-on-a-chip

ABSTRACT

Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed test-ing, low DfT overhead due to elimination of dedicated test circuitry and better power and thermal management during testing. However, such a self-test strategy might require a lengthy test program and might achieve a high enough fault coverage. We propose a DfT methodlogy to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core. This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance over-head. The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the program runtime, as compared to the case without instruction-level DfT.

REFERENCES

• 1: Wei-Cheng Lai , Angela Krstic , Kwang-Ting (Tim) Cheng, On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.15, April 30-May 04, 2000
• 2: Wei-Cheng Lai , Angela Krstic , Kwang-Ting (Tim) Cheng, Test Program Synthesis for Path Delay Faults in Microprocessor Cores, Proceedings of the 2000 IEEE International Test Conference, p.1080, October 03-05, 2000
• 3: The National Technology Roadmap for Semiconductors, Semiconductor Industry Association,1997.
• 4: Li Chen , Sujit Dey, DEFUSE: A Deterministic Functional Self-Test Methodology for Processors, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.255, April 30-May 04, 2000
• 5: D. Brahme and J.A. Abraham. Functional Testing of Microprocessors. IEEE Transactions on Computers, vol. C-33, pages. 475-485, 1984.
• 6: F. Distante and V. Piuri. Optimum Behavioral Test Procedure for VLSI Devices: A Simulated Annealing Approach. Proceedings of the IEEE International Conference on Computer Design, pages 31-35, 1986.
• 7: Jian Shen , Jacob A. Abraham, Native mode functional test generation for processors with applications to self test and design validation, Proceedings of the 1998 IEEE International Test Conference, p.990-999, October 18-22, 1998
• 8: Ken Batcher , Christos Papachristou, Instruction Randomization Self Test For Processor Cores, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.34, April 26-30, 1999
• 9: J. Lee and J.H. Patel. Architectural Level Test Generation for Microprocessors. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 13(10):1288-1300, October 1994.
• 10: David A. Patterson , John L. Hennessy, Computer organization & design: the hardware/software interface, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1993
• 11: PCI Special Interest Group, PCI Local Bus Specification, Revision 2.2, Porland, Oregon, Dec. 1998.
• 12: Virtual Socket Interface Alliance. VSI Alliance Virtual Component Interface Standard(OCB 2 1.0). March, 2000.
• 13: Zainalabedin Navabi, VHDL: Analysis and Modeling of Digital Systems, McGraw-Hill, Inc., New York, NY, 1997
• 14: M. Gumm. VLSI Design Course: VHDL-Modelling and Synthesis of the DLXS RISC Processor. University of Stuttgart, Germany, December 1995.
• 15: Jing-Reng Huang , Madhu K. Iyer , Kwang-Ting Cheng, A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs, Proceedings of the 19th IEEE VLSI Test Symposium, p.198, March 29-April 03, 2001
• 16: K.-T. Cheng, S. Devadas, and K. Keutzer. Delay-Fault Test Generation and Synthesis for Testability Under a Standard Scan Design Methodology. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(8):1217-1231, August 1993.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies
  B.8 Performance and Reliability

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Experimentation, Measurement, Performance, Reliability, Theory