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Formal property verification by abstraction refinement with formal, simulation and hybrid engines
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 38th annual Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 35 - 40  
Year of Publication: 2001
ISBN:1-58113-297-2
Authors
Dong Wang  Carnegie Mellon University
Pei-Hsin Jiang  Advanced Technology Group, Synopsys Inc.
James Kukula  Advanced Technology Group, Synopsys Inc.
Yunshan Zhu  Advanced Technology Group, Synopsys Inc.
Tony Ma  Advanced Technology Group, Synopsys Inc.
Robert Damiano  Advanced Technology Group, Synopsys Inc.
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 23,   Citation Count: 17
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ABSTRACT

We present RFN, a formal property verification tool based on abstraction refinement. Abstraction refinement is a strategy for property verification. It iteratively refines an abstract model to better approximate the behavior of the original design in the hope that the abstract model alone will provide enough evidence to prove or disprove the property.However, previous work on abstraction refinement was only demonstrated on designs with up to 500 registers. We developed RFN to verify real-world designs that may contain thousands of registers. RFN differs from the previous work in several ways. First, instead of relying on a single engine, RFN employs multiple formal verification engines, including a BDD-ATPG hybrid engine and a conventional BDD-based fixpoint engine, for finding error traces or proving properties on the abstract model. Second, RFN uses a novel two-phase process involving 3-valued simulation and sequential ATPG to determine how to refine the abstract model. Third, RFN avoids the weakness of other abstraction-refinement algorithms --- finding error traces on the original design, by utilizing the error trace of the abstract model to guide sequential ATPG to find an error trace on the original design.We implemented and applied a prototype of RFN to verify various properties of real-world RTL designs containing approximately 5,000 registers, which represents an order of magnitude improvement over previous results. On these designs, we successfully proved a few properties and discovered a design violation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  17

Collaborative Colleagues:
Dong Wang: colleagues
Pei-Hsin Jiang: colleagues
James Kukula: colleagues
Yunshan Zhu: colleagues
Tony Ma: colleagues
Robert Damiano: colleagues