Robust interfaces for mixed-timing systems with application to latency-insensitive protocols

ABSTRACT

This paper presents several low-latency mixed-timing FIFO designs that interface systems on a chip working at different speeds. The connected systems can be either synchronous or asynchronous. The design are then adapted to work between systems with very long interconnection delays, by migrating a single-clock solution by Carloni et al. (for “latency-insensitive” protocols) to mixed-timing domains. The new designs can be made arbitrarily robust with regard to metastability and interface operating speeds. Initial simulations for both latency and throughput are promising.

REFERENCES

• 1: David S. Bormann, Asynchronous Wrapper for Heterogeneous Systems, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.307, October 12-15, 1997
• 2: Luca P. Carloni , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.309-315, November 07-11, 1999, San Jose, California, United States
• 3: Daniel Marcos Chapiro, Globally-asynchronous locally-synchronous systems (performance, reliability, digital), 1985
• 4: Tiberiu Chelcea , Steven M. Nowick, Low-Latency Asynchronous FIFO's Using Token Rings, Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.210, April 02-06, 2000
• 5: Tiberiu Chelcea , Steven M. Nowick, A Low-Latency FIFO for Mixed-Clock Systems, Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00), p.119, April 27-28, 2000
• 6: J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev, "Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Transactions on Information and Systems, Vol. E80-D, Number 3, pp. 315-325, March 1997.
• 7: R.M. Fuhrer, S.M. Nowick, M. Theobald, N.K. Jha, B. Lin, L. Plana, "MINIMALIST: An environment for Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines," CUCS-020-99, Columbia University, Computer Science Department, 1999.
• 8: S. B. Furber, Asynchronous design, Low power design in deep submicron electronics, Kluwer Academic Publishers, Norwell, MA, 1997
• 9: J. Jex, C. Dike, K. Self, "Fully Asynchronous Interface with Programmable Metastability Settling Time Synchronizer", Patent No. 5,598,113 (Jan. 28, 1997).
• 10: Adaptive Synchronization, Proceedings of the International Conference on Computer Design, p.188, October 05-05, 1998
• 11: Mark R. Greenstreet, Implementing a STARI chip, Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors, p.38-43, October 02-04, 1995
• 12: C. L. Seitz, "System Timing", Introduction to VLSI Systems, Ch. 7, Addison-Wesley Pub. Co., 1980.
• 13: J. Seizovic, "Pipeline Synchronization", IEEE ASYNC'94 Symp., pp. 87-96.
• 14: M. Singh, S.M. Nowick, "MOUSETRAP: Ultra-High-Speed Transition-Signaling Asynchronous Pipelines", ACM TAU-00 Workshop, Austin, TX (Dec. 2000).
• 15: I. E. Sutherland, Micropipelines, Communications of the ACM, v.32 n.6, p.720-738, June 1989 [doi>10.1145/63526.63532]
• 16: Kenneth Y. Yun , Ryan P. Donohue, Pausible Clocking: A First Step Toward Heterogeneous Systems, Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors, p.118, October 07-09, 1996

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Standardization, Theory