LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs

ABSTRACT

This paper presents Lotterybus, a novel high-performance communication architecture for system-on-chip (SoC) designs. The Lotterybus architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of Lotterybus: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the Lotterybus architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4\% reduction in communication latencies over conventional on-chip communication architectures).

REFERENCES

• 1: Daniel D. Gajski , Frank Vahid , Sanjiv Narayan , Jie Gong, Specification and design of embedded systems, Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
• 2: Phillip A. Laplante, Real-Time Systems Design and Analysis: An Engineer's Handbook, IEEE Press, Piscataway, NJ, 1992
• 3: Henry Chang , Larry Cooke , Merrill Hunt , Grant Martin , Andrew J. McNelly , Lee Todd, Surviving the SOC revolution: a guide to platform-based design, Kluwer Academic Publishers, Norwell, MA, 1999
• 4: "IBM On-chip CoreConnect Bus Architecture." http://www.chips.ibm.com/products/coreconnect/index.html.
• 5: David Flynn, AMBA: Enabling Reusable On-Chip Designs, IEEE Micro, v.17 n.4, p.20-27, July 1997 [doi>10.1109/40.612211]
• 6: "Sonics Integration Architecture, Sonics Inc." http://www.sonicsinc.com.
• 7: "Peripheral Interconnect Bus Architecture." http://www.omimo.be.
• 8: B. Cordan, "An efficient bus architecture for system-on-a-chip design," in Proc. Custom Integrated Circuits Conf., pp. 623-626, 1999.
• 9: J. Turner and N. Yamanaka, "Architectural choices in large scale ATMswitches," IEICE Trans. on Communications, vol. E-81B, Feb. 1998.
• 10: "On chip bus attributes specification 1 OCB 1 1.0, On-chip bus DWG." http://www.vsi.org/library/specs/summary.htm.
• 11: "Open Core Protocol Specification - v1.0." http://www.sonics.com, Oct. 1999.
• 12: A. S. Tanenbaum, Computer networks, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 13: Nick McKeown , Martin Izzard , Adisak Mekkittikul , William Ellersick , Mark Horowitz, Tiny Tera: A Packet Switch Core, IEEE Micro, v.17 n.1, p.26-33, January 1997 [doi>10.1109/40.566194]
• 14: A. Smiljanic, "Flexible bandwidth allocation in terabit packet switches," in Proc. of Intl. Conf. on Telecommunication, June 2000.
• 15: H. Zhang, "Service disciplines for guaranteed performance service in packetswitching networks," Proc. of IEEE, vol. 83, Oct. 1995.
• 16: A. C. Waldspurger and W. E. Weihl, "Lottery scheduling: Flexible proportionalshare resource management," in Proc. Symp. on Operating Systems Design and Implementation, pp. 1-12, 1994.
• 17: J. Buck and S. Ha and E. A. Lee and D. D. Masserchmitt, "Ptolemy: A framework for simulating and prototyping heterogeneous systems," International Journal on Computer Simulation, Special Issue on Simulation Software Management, vol. 4, pp. 155-182, Apr. 1994.
• 18: Felice Balarin , Massimiliano Chiodo , Paolo Giusto , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli , Ellen Sentovich , Kei Suzuki , Bassam Tabbara, Hardware-software co-design of embedded systems: the POLIS approach, Kluwer Academic Publishers, Norwell, MA, 1997
• 19: Kanishka Lahiri , Sujit Dey , Anand Raghunathan, Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures, Proceedings of the The 14th International Conference on VLSI Design (VLSID '01), p.29, January 03-07, 2001
• 20: "CBC9-VX datasheet." http://www.necel.com.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Experimentation, Measurement, Performance, Theory