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ABSTRACT
Nanometer IC technologies are on the horizon. They promise a lot. But will cost a lot as well. Therefore, we need to ask today: How may the billions of dollars, that we will have to spent on nanometer-fablines, affect IC design domain? This paper attempts to address the above question by analyzing the design-manufacturing interface. A partial answer is derived from a simple transistor cost model proposed in the body of the paper.
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Bo Hu , Hailin Jiang , Qinghua Liu , Malgorzata Marek-Sadowska, Synthesis and placement flow for gain-based programmable regular fabrics, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
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Matthew M. Ziegler , Gary S. Ditlow , Stephen V. Kosonocky , Zhenyu (Jerry) Qi , Mircea R. Stan, Structured and tuned array generation (STAG) for high-performance random logic, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
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