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Improving Java performance using hardware translation
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Source International Conference on Supercomputing archive
Proceedings of the 15th international conference on Supercomputing table of contents
Sorrento, Italy
Pages: 427 - 439  
Year of Publication: 2001
ISBN:1-58113-410-X
Authors
Ramesh Radhakrishnan  Laboratory for Computer Architecture, Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Ravi Bhargava  Laboratory for Computer Architecture, Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Lizy K. John  Laboratory for Computer Architecture, Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

State of the art Java Virtual Machines with Just-In-Time (JIT) compilers make use of advanced compiler techniques, run-time profiling and adaptive compilation to improve performance. However, these techniques for alleviating performance bottlenecks are more effective in long running workloads, such as server applications. Short running Java programs, or client workloads, spend a large fraction of their execution time in compilation instead of useful execution when run using JIT compilers. In short running Java programs, the benefits of runtime translation do not compensate for the overhead.

We propose using hardware support to perform efficient Java translation coupled with a light weight run time environment. The additional hardware performs the translation of Java bytecodes to native code, thus eliminating much of the overhead of software translation. A translate d code buffer is used to hold the translated code, enabling reuse at the byte code level. The proposed hardware can be used in any general purpose processor without degrading performance of native code. The proposed technique is extremely effective for short running client workloads. A performance improvement of 2.8 times to 7.7 times over a software interpreter is achieved. When compared to a JIT compiler all SPECjvm98 benchmarks except one show a performance improvement ranging from. 2.7 times to 5.0 times. A performance degradation (0.58 times) is observed for one benchmark which is long running. Allowing hardware translation to perform optimizations similar to JIT compilers and Java processors will execute long running programs more efficiently and provide speedups similar to that of client workloads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
Ramesh Radhakrishnan: colleagues
Ravi Bhargava: colleagues
Lizy K. John: colleagues