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Multiplex: unifying conventional and speculative thread-level parallelism on a chip multiprocessor
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Source International Conference on Supercomputing archive
Proceedings of the 15th international conference on Supercomputing table of contents
Sorrento, Italy
Pages: 368 - 380  
Year of Publication: 2001
ISBN:1-58113-410-X
Authors
Chong-Liang Ooi  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Seon Wook Kim  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Il Park  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Rudolf Eigenmann  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Babak Falsafi  Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
T. N. Vijaykumar  School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 31,   Citation Count: 14
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ABSTRACT

Recent proposals for Chip Multiprocessors (CMPs) advocate speculative, or implicit, threading in which the hardware employs prediction to peel off instruction sequences (i.e., implicit threads) from the sequential execution stream and speculatively executes them in parallel on multiple processor cores. These proposals augment a conventional multiprocessor, which employs explicit threading, with the ability to handle implicit threads. Current proposals focus on only implicitly-threaded code sections. This paper identifies, for the first time, the issues in combining explicit and implicit threading. We present the Multiplex architecture to combine the two threading models. Multiplex exploits the similarities between implicit and explicit threading, and provides a unified support for the two threading models without additional hardware. Multiplex groups a subset of protocol states in an implicitly-threaded CMP to provide a write-invalidate protocol for explicit threads.

Using a fully-integrated compiler infrastructure for automatic generation of Multiplex code, this paper presents a detailed performance analysis for entire benchmarks, instead of just implicitly-threaded sections, as done in previous papers. We show that neither threading models alone performs consistently better than the other across the benchmarks. A CMP with four dual-issue CPUs achieves a speedup of 1.48 and 2.17 over one dual-issue CPU, using implicit-only and explicit-only threading, respectively. Multiplex matches or outperforms the better of the two threading models for every benchmark, and a four-CPU Multiplex achieves a speedup of 2.63. Our detailed analysis indicates that the dominant overheads in an implicitly-threaded CMP are speculation state overflow due to limited L1 cache capacity, and load imbalance and data dependences in fine-grain threads.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY  14

Collaborative Colleagues:
Chong-Liang Ooi: colleagues
Seon Wook Kim: colleagues
Il Park: colleagues
Rudolf Eigenmann: colleagues
Babak Falsafi: colleagues
T. N. Vijaykumar: colleagues