Reducing the complexity of the issue logic

ABSTRACT

The issue logic of dynamically scheduled superscalar processors is one of their most complex and power-consuming parts. In this paper we present alternative issue-logic designs that are much simpler than the traditional scheme while they retain most of its ability to exploit ILP. These alternative schemes are based on the observation that most values produced by a program are used by very few instructions, and the latencies of most operation are deterministic.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES

Additional Classification:
  D. Software
  D.1 PROGRAMMING TECHNIQUES

General Terms:
Management, Performance

Keywords:
complexity-effective design, instruction issue logic, out-of-order issue, wide-issue superscalar