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ABSTRACT
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache performance due to non-locality of data references. Despite this, there is no published research deriving or measuring these qualities. Utilizing the previously developed Berkeley Multimedia Workload, we present the results of execution driven cache simulations with the goal of aiding future media processing architecture design. Our analysis examines the differences between multimedia and traditional applications in cache behavior. We find that multimedia applications actually exhibit lower instruction miss ratios and comparable data miss ratios when contrasted with other widely studied workloads. In addition, we find that longer data cache line sizes than are currently used would benefit multimedia processing.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
|
| |
2
|
Advanced Micro Devices, Inc., "AMD Athlon Processor x86 Code Optimization Guide," Publication #22007G/0, April 2000, http://www.amd.com/products/cpg/athlon/techdocs/pdf/ 22007.pdf, retrieved April 24, 2000
|
| |
3
|
Todd M. Austin, Doug Burger, Manoj Franklin, Scott Breach, Kevin Skadron, "The SimpleScalar Architectural Research Tool Set," http://www.cs.wisc.edu/~mscalar/ simplescalar.html, retrieved April 24, 2000
|
| |
4
|
Vasudev Bhaskaran, Konstantinos Konstantinides, and Balas Natarajan, "Multimedia architectures: from desktop systems to portable appliances," Proc. Multimedia Hardware Architectures, San Jose, California, February 2-14, 1997, SPIE Vol. 3021, pp. 14-25
|
 |
5
|
Anita Borg , R. E. Kessler , David W. Wall, Generation and analysis of very long address traces, Proceedings of the 17th annual international symposium on Computer Architecture, p.270-279, May 28-31, 1990, Seattle, Washington, United States
|
| |
6
|
Tom Burd, "CPU Info Center: General Processor Info," http://bwrc.eecs.berkeley.edu/CIC/summary/local/summary.pdf, retrieved April 24, 2000
|
 |
7
|
|
 |
8
|
D. W. Clark , P. J. Bannon , J. B. Keller, Measuring VAX 8800 performance with a histogram hardware monitor, Proceedings of the 15th Annual International Symposium on Computer architecture, p.176-185, May 30-June 02, 1988, Honolulu, Hawaii, United States
|
| |
9
|
Thomas M. Conte , Pradeep K. Dubey , Matthew D. Jennings , Ruby B. Lee , Alex Peleg , Salliah Rathnam , Mike Schlansker , Peter Song , Andrew Wolfe, Challenges to Combining General-Purpose and Multimedia Processors, Computer, v.30 n.12, p.33-37, December 1997
[doi> 10.1109/2.642799]
|
 |
10
|
|
| |
11
|
Rita Cucchiara, Massimo Piccardi, Andrea Prati, "Exploiting Cache in Multimedia," Proc. of IEEE Multimedia Systems '99 Vol. 1, Florennce, Italy, July 7-11 1999, pp. 345-350
|
| |
12
|
Digital Equipment Corporation, ATOM Reference Manual, http://www.partner.digital.com/www-swdev/files/DECOSF1/ Docs/Other/ATOM/ref.ps retrieved April 24, 2000
|
| |
13
|
|
| |
14
|
Jan Edler, Mark D. Hill, "Dinero IV Trace-Driven Uniprocessor Cache Simulator," http://www.neci.nj.nec.com/ homepages/edler/d4/, retrieved Apil 24, 2000
|
| |
15
|
J. Gee, A. J. Smith, "The Performance Impact of Vector Processor Caches," Proc. 25th Hawii Int'l Conf. on System Sciences, Vol. 1, January 1992, pp. 437-449
|
| |
16
|
|
 |
17
|
|
| |
18
|
|
| |
19
|
Intel Corporation, "Accelerated Graphics Port Interface Specification v2.0," May 4, 1998, http://developer.intel.com/ technology/agp/, retrieved April 24, 2000
|
| |
20
|
Richard Eugene Kessler, "Analysis of Multi-Megabyte Secondary CPU Cache Memories," University of Wisconsin-Madison Computer Sciences Technical Report #1032, July 1991
|
| |
21
|
Ichiro Kuroda, Takao Nishitani, "Multimedia Processors," Proc. IEEE, Vol. 86, No. 6, June 1998, pp. 1203-1221
|
| |
22
|
|
| |
23
|
Kim Noer, "Heat Dissipation Per Square Millimeter Die Size Specifications," http://home.worldonline.dk/~noer/, retrieved April 24, 2000
|
 |
24
|
S. Prybylski , M. Horowitz , J. Hennessy, Performance tradeoffs in cache design, Proceedings of the 15th Annual International Symposium on Computer architecture, p.290-298, May 30-June 02, 1988, Honolulu, Hawaii, United States
|
| |
25
|
Scott Rixner , William J. Dally , Ujval J. Kapasi , Brucek Khailany , Abelardo López-Lagunas , Peter R. Mattson , John D. Owens, A bandwidth-efficient architecture for media processing, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.3-13, November 1998, Dallas, Texas, United States
|
 |
26
|
|
| |
27
|
|
| |
28
|
|
| |
29
|
|
 |
30
|
|
 |
31
|
|
| |
32
|
|
| |
33
|
Alan Jay Smith, "Trace Driven Simulation in Research on Computer Architecture and Operating Systems," Proc. Conference on New Directions in Simulation for Manufacturing and Communications, Tokyo, Japan, August 1994, pp. 43-49
|
 |
34
|
|
| |
35
|
Pieter Struik, Pieter van der Wolf, Andy D. Pimentel, "A Combined Hardware/Software Solution for Stream Prefetching in Multimedia Applications," Proc. 10th Annual Symp. on Electronic Imaging, San Jose, California, January 1998, pp. 120-130
|
 |
36
|
|
| |
37
|
|
 |
38
|
|
 |
39
|
|
| |
40
|
Glenn Ammons, Tom Ball, Mark Hill, Babak Falsafi, Steve Huss-Lederman, James Larus, Alvin Lebeck, Mike Litzkow, Shubhendu Mukherjee, Steven Reinhardt, Madhusudhan Talluri, and David Wood, "WARTS: Wisconsin Architectural Research Tool Set," http://www.cs.wisc.edu/~larus/ warts.html, retrieved April 24, 2000
|
| |
41
|
Daniel F. Zucker, Michael J. Flynn, and Ruby B. Lee, "A Comparison of Hardware Prefetching Techniques for Multimedia Benchmarks," Proc. 3rd IEEE Int'l Conference on Multimedia Computing and Systems, Hiroshima, Japan, June 17-23, 1996, pp. 236-244
|
|