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Eliminating redundancies in sum-of-product array computations
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Source International Conference on Supercomputing archive
Proceedings of the 15th international conference on Supercomputing table of contents
Sorrento, Italy
Pages: 65 - 77  
Year of Publication: 2001
ISBN:1-58113-410-X
Authors
Steven J. Deitz  University of Washington, Dept of CSE; Box 352350, Seattle, WA
Bradford L. Chamberlain  University of Washington, Dept of CSE; Box 352350, Seattle, WA
Lawrence Snyder  University of Washington, Dept of CSE; Box 352350, Seattle, WA
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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ABSTRACT

Array programming languages such as Fortran 90, High Performance Fortran and ZPL are well-suited to scientific computing because they free the scientist from the responsibility of managing burdensome low-level details that complicate programming in languages like C and Fortran 77. However, these burdensome details are critical to performance, thus necessitating aggressive compilation techniques for their optimization. In this paper, we present a new compiler optimization called Array Subexpression Elimination (ASE) that lets a programmer take advantage of the expressibility afforded by array languages and achieve enviable portability and performance. We design a set of micro-benchmarks that model an important class of computations known as stencils and we report on our implementation of this optimization in the context of this micro-benchmark suite. Our results include a 125% improvement on one of these benchmarks and a 50% average speedup across the suite. Also we show a speedup of 32% improvement on the ZPL port of the NAS MG Parallel Benchmark and a 29% speedup over the hand-optimized Fortran version. Further, the compilation time is only negligibly affected.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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D. Bailey, E. Barszcz, J. Barton, D. Browning, R. Carter, L. Dagum, R. Fatoohi, S. Fineberg, P. Frederickson, T. Lasinski, R. Schreiber, H. Simon, V. Venkatakrishnan, and S. Weeratunga. The NAS parallel benchmarks (94). Technical report, RNR Technical Report RNR-94-007, March 1994.
 
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D. Bailey, T. Harris, W. Saphir, R. van der Wijngaart, A. Woo, and M. Yarrow. The NAS parallel benchmarks 2.0. Technical report, NAS Report NAS-95-020, December 1995.
 
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R. G. Brickner, K. Holian, B. Thiagarajan, and S. L. Johnson. A stencil compiler for the connection machine model cm-5. Technical report, Center for Research onParallel Computation CRPC-TR94457, June 1994.
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9
 
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C. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, M. E. Hopkins, and P. W. Markstein. Register allocation via coloring. Computer Languages, 6:45-57, January 1981.
 
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A. L. Fisher and P. T. Highnam. Communication and code optimization in simd programs. In International Conference onParallel Processing, 1988.
 
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A. L. Fisher, J. Leon, and P. T. Highnam. Design and performance of an optimizing simd compiler. In Frontiers of Massively Parallel Computation, 1990.
 
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High Performance Fortran Forum. High Performance Fortran Langauge Specification, Version 2.0. January 1997.
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L. Snyder. Programming Guide to ZPL. MIT Press, 1999.


Collaborative Colleagues:
Steven J. Deitz: colleagues
Bradford L. Chamberlain: colleagues
Lawrence Snyder: colleagues