ACM Home Page
Please provide us with feedback. Feedback
Analytical cache models with applications to cache partitioning
Full text PdfPdf (854 KB)
Source International Conference on Supercomputing archive
Proceedings of the 15th international conference on Supercomputing table of contents
Sorrento, Italy
Pages: 1 - 12  
Year of Publication: 2001
ISBN:1-58113-410-X
Authors
G. Edward Suh  Laboratory for Computer Science, Massachusetts Institute of Technology Cambridge, MA
Srinivas Devadas  Laboratory for Computer Science, Massachusetts Institute of Technology Cambridge, MA
Larry Rudolph  Laboratory for Computer Science, Massachusetts Institute of Technology Cambridge, MA
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 80,   Citation Count: 16
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/377792.377797
What is a DOI?

ABSTRACT

An accurate, tractable, analytic cache model for time-shared systems is presented, which estimates the overall cache miss-rate of a multiprocessing system with any cache size and time quanta. The input to the model consists of the isolated miss-rate curves for each process, the time quanta for each of the executing processes, and the total cache size. The output is the overall miss-rate. Trace-driven simulations demonstrate that the estimated miss-rate is very accurate. Since the model provides a fast and accurate way to estimate the effect of context switching, it is useful for both understanding the effect of context switching on caches and optimizing cache performance for time-shared systems. A cache partitioning mechanism is also presented and is shown to improve the cache miss-rate up to 25% over the normal LRU replacement policy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
Cumpaq. Cumpaq A1phaStatiun family.
 
3
 
4
 
5
C. Freeburit. The hewlett packard PA-RISC 8500 processor. TechiticM report, Itewlett Packard Laboratories, Oct. 1998.
6
 
7
J. L. Heititiitg. SPEC CPU2000: Measuriitg CPU performaitce iit the Itew Itfilleititium. IEEE Computer, July 2000.
8
 
9
D. B. Kirk. Process depeitdeitt static cache partitioitiitg for reM-time systems. IIt Real-Time Systems Symposium, 1988.
 
10
11
 
12
P. Magitussoit aitd B. Weriter. Efficieitt memory simulatioit iit SimICS. lit 28th Annual Simulation Symposium, 1995.
 
13
MIPS Techitologies, IItc. MIPS RIO000 Microprocessor" User's Manual, 1996.
14
 
15
J. Muoz. Data-Intensive Systems Benchmark Suite Analysis and Specification. http://www.aec.com/projectweb/dis, Juite 1999.
 
16
 
17
 
18
 
19
G. E. Suh aitd L. Rudolph. Set-associative cache models for time-shared systems. Techitical Report CSG Memo 433, Massachusetts IItstitute of Techitology, 2001.
20
 
21
 
22
23
24
25
 
26

CITED BY  16

Collaborative Colleagues:
G. Edward Suh: colleagues
Srinivas Devadas: colleagues
Larry Rudolph: colleagues