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A parallel processor architecture for graphics arithmetic operations
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Source International Conference on Computer Graphics and Interactive Techniques archive
Proceedings of the 14th annual conference on Computer graphics and interactive techniques table of contents
Pages: 197 - 204  
Year of Publication: 1987
ISBN:0-89791-227-6
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Author
John G. Torborg  Raster Technologies, Inc., Westford, MA
Sponsor
SIGGRAPH: ACM Special Interest Group on Computer Graphics and Interactive Techniques
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 6,   Downloads (12 Months): 43,   Citation Count: 17
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ABSTRACT

Interactive 3D graphics applications require significant arithmetic processing to handle complex models, particularly if realistic rendering techniques are used. Current semiconductor technology cannot provide the necessary performance without some form of multi-processing.This paper describes a graphics processor architecture which can be configured with an arbitrary number of identical processors operating in parallel. Each of the parallel processors can be programmed identically as if it were a single processor system, substantially simplifying software development and allowing complex rendering functions to take advantage of the multiple processors. The architecture described is able to achieve extremely high performance while allowing the price/performance of the system to be optimized for a given application.Techniques are described for handling graphics command distribution, sequencing of commands which must be processed in order, parallel processing of graphics primitive picking, and handling inquiry (read-back) commands.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Fuchs, H. and Poulton, J., "Pixel-Planes: A VLS1-Oriented Design for a Raster Graphics Engine," VLSI Design, No. 3 (1981), 20.
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Torborg, John G., "Computer Graphics System Having Arbitrary Number of Parallel Arithmetic Processors," US Patent Application, (1987).
 
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van Dam. A., et. al., "PHIGS+ Functional Description Rev. 2," Jointly developed PHIGS+ specification. (1987) Contact Andries van Dam - Committee Chairman, Stellar Computer Inc., 100 Wells Ave., Newton, MA, 02159. (1987).

CITED BY  17