| Parameterised system design based on genetic algorithms |
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International Conference on Hardware Software Codesign
archive
Proceedings of the ninth international symposium on Hardware/software codesign
table of contents
Copenhagen, Denmark
Pages: 177 - 182
Year of Publication: 2001
ISBN:1-58113-364-2
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Authors
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Giuseppe Ascia
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Dipartimento di Ingegneria, Informatica e delle, Telecomunicazioni, Università di Catania, V.le Andrea Doria, 6, 95125 Catania - Italy
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Vincenzo Catania
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Dipartimento di Ingegneria, Informatica e delle, Telecomunicazioni, Università di Catania, V.le Andrea Doria, 6, 95125 Catania - Italy
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Maurizio Palesi
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Dipartimento di Ingegneria, Informatica e delle, Telecomunicazioni, Università di Catania, V.le Andrea Doria, 6, 95125 Catania - Italy
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Downloads (6 Weeks): 7, Downloads (12 Months): 16, Citation Count: 5
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ABSTRACT
A recent reduction in the time to market has led to the development of a new approach to IP-based design in which a highly parametric pre-designed system-on-a-chip is configured according to the application it will have to execute. The greatest problems in this area regard exploration of the range of possible system configurations in search of the optimal configuration for a given system. There are, in fact, a number of parameters involved (bus sizes, cache configurations, software algorithms, etc.), each of which has a great impact on design constraints such as area, power and performance. An exhaustive analysis of all possible configurations is thus computationally unfeasible. In this paper we propose using genetic algorithms to determine the optimal configuration for a highly parametric system. The approach is applied to the search for the optimal configuration (in terms of area, power and mean access time) of a memory hierarchy involved in a given application.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CPU info center. http://mm, eecs. berkeley, edu/CIC/.
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2
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Trace database, Parallel Architecture Research Laboratory, New Mexico State University. hl;tp://tracsbaso.nmsu.edu/.
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3
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TMS320C6211 cache analysis. Texas Instruments, Sept. 1998.
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4
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5
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C. A. C. Coello. Treating constraints as objectives for single.objective evolutionary optimization. Technical report, Laboratorio Nacional de Informatica Avanzada, Rebsmen 80, Xalapa, Veracruz 91090, Mexico, 2000.
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6
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J. Edler and M. D. Hill. Dinero IV, release 7. http://etw.cs.gisc.odu/markhill/DinorolVl 6 Feb. 1998.
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7
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8
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C. M. Fonseca and P. J. Fleming. An overview of evolutionary algorithms in multiobjective optimization. Evolutionary Computation, 3(1):1-16, 1995.
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9
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10
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11
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12
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Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
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13
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14
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|
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15
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J. J. Grefenstette. A User's Guide to GENESIS, Oct. 1990.
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16
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|
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17
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D. Krfining and S. M. Miiller. The impact of write-bach on the cache performance. In Prec. 18th IASTED International Conference on Applied lnformatics, lnnsbruck (AI'2000), pages 213-217. ACTA Press, 2000.
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18
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19
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20
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G. Reinman and N. Jouppi. An integrated cache timing and power model. Technicd report, COMPAQ Western Research Lab, Palo Alto, 1999.
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21
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C. Romero, M. "lmiz, and D. Jones. Goal programming, compromise programming and reference point method formulations: linkages and utility interpretations. Journal of the Operational Research 8ociety, (49):986-991, 1998.
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22
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Synopsys, Inc. CoWare, Inc. Frontier Design, Inc. SystemC 0.91 User's Guide.
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23
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CITED BY 5
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Giuseppe Ascia , Vincenzo Catania , Alessandro G. Di Nuovo , Maurizio Palesi , Davide Patti, Efficient design space exploration for application specific systems-on-a-chip, Journal of Systems Architecture: the EUROMICRO Journal, v.53 n.10, p.733-750, October, 2007
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