Designing domain-specific processors

ABSTRACT

We present a semi-automated method for the detection and exploitation of application domain specific instruction set extensions for embedded (VLIW) processors. It consists of three steps: the first step detects frequently occurring operation patterns, in the second step, the patterns are grouped and implemented in a number of Special Function Units (SFUs) and the third step incorporates the custom operations into the code generation process.

Experiments show that the SFUs generated and exploited with our methodology can result in architectures that perform up to 30% better than architectures of the same cost without SFUs.

REFERENCES

• 1: Tom R. Halfhill. 1999 review: Embedded market breaks new ground. Embedded Processor Watch, 82, January 2000.
• 2: K. Keutzer, DAGON: technology binding and local optimization by DAG matching, Proceedings of the 24th ACM/IEEE conference on Design automation, p.341-347, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37940]
• 3: It. Rudell. Logic synthesis for visi design. Technical Report UCB/ERL M89/49, University of California at Berkeley, April 1989.
• 4: Alfred V. Aho , Mahadevan Ganapathi , Steven W. K. Tjiang, Code generation using tree matching and dynamic programming, ACM Transactions on Programming Languages and Systems (TOPLAS), v.11 n.4, p.491-516, Oct. 1989 [doi>10.1145/69558.75700]
• 5: Christopher W. Fraser and Todd A. Proebsting. Custom instruction sets for code compression, not published, 1995.
• 6: Frederick Onion, Alexandru Nicolau, and Nikil Dutt. Compiler Feedback in ASIP Design. Technical report, University of California, Irvine, September 1994.
• 7: Marnix Arnold , Henk Corporaal, Automatic detection of recurring operation patterns, Proceedings of the seventh international workshop on Hardware/software codesign, p.22-26, March 1999, Rome, Italy [doi>10.1145/301177.301192]
• 8: Yiannakis Sazeides , Stamatis Vassiliadis , James E. Smith, The performance potential of data dependence speculation & collapsing, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.238-247, December 02-04, 1996, Paris, France
• 9: Bruce K. Holmer, A tool for processor instruction set design, Proceedings of the conference on European design automation, p.150-155, September 19-23, 1994, Grenoble, France
• 10: Ing-Jer Huang , Alvin M. Despain, Synthesis of instruction sets for pipelined microprocessors, Proceedings of the 31st annual conference on Design automation, p.5-11, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196250]
• 11: Stan Liao , Srinivas Devadas , Kurt Keutzer , Steve Tjiang, Instruction selection using binate covering for code size optimization, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.393-399, November 05-09, 1995, San Jose, California, United States
• 12: Clifford Liem, Trevor May, and Pierre Paulin. Instruction-set matching and selection for dsp and asip code generation. In Proceedings of EDAC-BTCoEUROASICS pages 31-37, 1994.
• 13: R. Leupers , P. Marwedel, Instruction selection for embedded DSPs with complex instructions, Proceedings of the conference on European design automation, p.200-205, September 1996, Geneva, Switzerland
• 14: Marnix Arnold. lnatruction Set Eztension for Embedded Processors. PhD thesis, Delft University of Technology, March 2001. ISBN 90-9014523-0.
• 15: Jan Hoogerbrugge. Code generation for Transport Triggered Architectures. PhD thesis, Delft Univ. of Technology, February 1996. ISBN 90-9009002-9.
• 16: Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
• 17: S. Vassiliadis , J. Phillips , B. Blaner, Interlock Collapsing ALU's, IEEE Transactions on Computers, v.42 n.7, p.825-839, July 1993 [doi>10.1109/12.237723]
• 18: Troy N. Hicks, Richard E. Fry, and Paul E. Harvey. Power2 floating-point unit: Architecture and implementation. http://www.austin.ibm.com/tech/fpu.htmi, 1994.
• 19: William L. Lynch , Gary Lauterbach , Joseph I. Chamdani, Low load latency through sum-addressed memory (SAM), Proceedings of the 25th annual international symposium on Computer architecture, p.369-379, June 27-July 02, 1998, Barcelona, Spain

INDEX TERMS

Primary Classification:
  D. Software
  D.4 OPERATING SYSTEMS

Additional Classification:
  F. Theory of Computation
  F.1 COMPUTATION BY ABSTRACT DEVICES

General Terms:
Design, Management

Keywords:
design space exploration, instruction set synthesis