Optimal test access architectures for system-on-a-chip

ABSTRACT

Test access is a major problem for core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. An efficient test access architecture should also reduce test cost by minimizing test application time. We address several issues related to the design of optimal test access architectures that minimize testing time., including the assignment of cores to test buses, distribution of test data width between multiple test buses, and analysis of test data width required to satisfy an upper bound on the testing time. Even though the decision versions of all these problems are shown to be NP-complete, they can be solved exactly for practical instances using integer linear programming (ILP). As a case study, the ILP models for two hypothetical but nontrivial systems are solved using a public-domain ILP software package.

REFERENCES

• 1: Joep Aerts , Erik Jan Marinissen, Scan chain design for test time reduction in core-based ICs, Proceedings of the 1998 IEEE International Test Conference, p.448-457, October 18-22, 1998
• 2: BERKELAAR, M. 1999. lpsolve, version 2.0. Department of Mathematics and Computing Science, Eindhoven University of Technology, Eindhoven, Netherlands. E-mail: [e-mail]
• 3: BRGLEZ, F., BRYANT, D., AND KOZMINSKI, K. 1989. Combinational profiles of sequential benchmark circuits. In Proceedings of the IEEE International Symposium on Circuits and Systems (Portland, OR, May). IEEE Press, Piscataway, NJ, 1929-1934. ACM Transactions on Design Automation of Electronic Systems, Vol. 6, No. 1, January 2001.
• 4: BRGLEZ,F.AND FUJIWARA, H. 1985. A neural netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Proceedings of IEEE International Symposium on Circuits and Systems. IEEE Computer Society, Washington, DC, 695-698.
• 5: CHAKRABARTY, K. 2000a. Test scheduling for core-based systems using mixed-integer linear programming. IEEE Trans. Comput.-Aided Des. 19, 10 (Oct.), 1163-1174.
• 6: Krishnendu Chakrabarty, Design of system-on-a-chip test access architectures under place-and-route and power constraints, Proceedings of the 37th conference on Design automation, p.432-437, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337531]
• 7: Krishnendu Chakrabarty, Test scheduling for core-based systems, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.391-394, November 07-11, 1999, San Jose, California, United States
• 8: FOURER, R., GAY,D.M.,AND KERNIGHAN, B. W. 1993. AMPL: A Modeling Language for Mathematical Programming. Duxbury Press, Boston, MA.
• 9: GAMS DEVELOPMENT CORPORATION. 1993. GAMS: A User's Guide. Boyd and Fraser Publishing Co., Danvers, MA.
• 10: Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
• 11: Indradeep Ghosh , Sujit Dey , Niraj K. Jha, A fast and low cost testing technique for core-based system-on-chip, Proceedings of the 35th annual conference on Design automation, p.542-547, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277190]
• 12: Indradeep Ghosh , Niraj K. Jha , Sujit Dey, A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems, Proceedings of the IEEE International Test Conference, p.50-59, November 03-05, 1997
• 13: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
• 14: IMMANENI,V.AND RAMAN, S. 1990. Direct access test scheme: Design of block and core cells for embedded ASICs. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, CA, 488-492.
• 15: Erik Jan Marinissen , Maurice Lousberg, The Role of Test Protocols in Testing Embedded-Core-Based System ICs, Proceedings of the 1999 IEEE European Test Workshop, p.70, September 24-27, 1999
• 16: Erik Jan Marinissen , Yervant Zorian , Rohit Kapur , Tony Taylor , Lee Whetsel, Towards a Standard for Embedded Core Test: An Example, Proceedings of the 1999 IEEE International Test Conference, p.616, September 28-30, 1999
• 17: Erik Jan Marinissen , Robert G. J. Arendsen , Gerard Bos , Hans Dingemanse , Maurice Lousberg , Clemens Wouters, A structured and scalable mechanism for test access to embedded reusable cores, Proceedings of the 1998 IEEE International Test Conference, p.284-293, October 18-22, 1998
• 18: Makoto Sugihara , Hiroshi Date , Hiroto Yasuura, A novel test methodology for core-based system LSIs and a testing time minimization problem, Proceedings of the 1998 IEEE International Test Conference, p.465, October 18-22, 1998
• 19: WILLIAMS, H. P. 1985. Model Building in Mathematical Programming. 2nd ed. John Wiley, New York, NY.
• 20: Prab Varma , Sandeep Bhatia, A structured test re-use methodology for core-based system chips, Proceedings of the 1998 IEEE International Test Conference, p.294-302, October 18-22, 1998
• 21: Yervant Zorian , Erik Jan Marinissen , Sujit Dey, Testing embedded-core based system chips, Proceedings of the 1998 IEEE International Test Conference, p.130, October 18-22, 1998
• 22: Yervant Zorian, Test Requirements for Embedded Core-Based Systems and IEEE P1500, Proceedings of the IEEE International Test Conference, p.191-199, November 03-05, 1997

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Reliability