Effectiveness of the ASIP design system PEAS-III in design of pipelined processors

ABSTRACT

In this paper, the effectiveness of the ASIP (Application Specific Instruction set Processor) design system PEAS-III is evaluated through experiments. Examples in experiments are a MIPS R3000 compatible processor, DLX, a simple RISC controller, and PEAS-I core. While they are simple in-order pipelined processors, they have enough facilities for real embedded system design. Through experiments, easiness of design and modification for improvement and design quality in terms of performance and hardware cost are discussed. It has been confirmed that the design method used in PEAS-III is effective to design space exploration for simple pipelined processors.

REFERENCES

• 1: Ricardo E. Gonzalez, Xtensa: A Configurable and Extensible Processor, IEEE Micro, v.20 n.2, p.60-70, March 2000 [doi>10.1109/40.848473]
• 2: Makiko Itoh, Yoshinori Takeuchi, Masaharu Imai, and Akichika Shiomi, "Synthesizable HDL generation for pipelined processors from a micro-operation description," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E83-A, no. 3, pp. 394-400, Mar. 2000.
• 3: PEAS-III: An ASIP Design Environment, Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, p.430, September 17-20, 2000
• 4: Masaharu Imai, Yoshinori Takeuchi, Takafumi Morifuji, and Eiichiro Shigehara, "Flexible hardware model: A new paradigm for design reuse," in APCHDL '98, Seoul, Korea, July 1998, Invited Talk.
• 5: Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
• 6: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 7: Jun Sato, Alauddin Y. Alomary, Yoshimichi Honma, Takeharu Nakata, Akichika Shiomi, Nobuyuki Hikichi, and Masaharu Imai, "PEAS-I: A hardware/software co-design system for ASIP development," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E77-A, no. 3, pp. 483-491, Mar. 1994.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.3 Other Architecture Styles
          Subjects: Pipeline processors

Additional Classification:
  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Experimentation, Performance, Theory