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Efficient global fanout optimization algorithms
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 571 - 576  
Year of Publication: 2001
ISBN:0-7803-6634-4
Author
Rajeev Murgai  Fujitsu Laboratories of America, Inc., California
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

Fanout optimization is a fundamental problem in timing optimization. Most of the research has focused on the fanout optimization problem for a single net (or the local fanout optimization problem - LFO). The real goal, however, is to optimize the delay through the entire circuit by fanout optimization incurring minimum area penalty and without violating the pin loading constraints. This is known as the global fanout optimization (GFO) problem. In this paper, we show that the techniques proposed so far in the literature are either impractical or ineffective for large designs. We propose simple yet efficient and effective schemes for GFO and show that they outperform the "nearly-optimum" reverse topological (RT) algorithm [9] on large industrial designs. One of these schemes yields only 0.3% worse circuit delay on average, but incurs only 18.5% of the area penalty as compared to the RT algorithm and is about 3 times faster. A popularly used mincut-based strategy [7] was not found to be effective.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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G. De Micheli. Performance-Oriented Synthesis fo Large-Scale Domino CMOS Circuits. IEEE Transactions on Computer-Aided Design, CAD-6(5):751-765, 1987.
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Lukas P. P. P. van Ginneken. Buffer Placement in Distributed RC-tree Networks for Minimum Elmore DElay. In ISCAS, pages 865-868, 1990.
 
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K. J. Singh, a. R. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli. Timing Optimization of Combinational Logic. In ICCAD, pages 282-285. IEEE, 1988.
 
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