ACM Home Page
Please provide us with feedback. Feedback
Functional extension of structural logic optimization techniques
Full text PdfPdf (104 KB)
Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 467 - 472  
Year of Publication: 2001
ISBN:0-7803-6634-4
Authors
J. A. Espejo  Universidad Carlos III de Madrid
L. Entrena  Universidad Carlos III de Madrid
E. San Millán  Universidad Carlos III de Madrid
E. Oliás  Universidad Carlos III de Madrid
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Citation Count: 1
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/370155.370514
What is a DOI?

ABSTRACT

This work provides a generalization of structural logic optimization methods to general boolean networks. With this generalization, the nodes of the network are no longer restricted to simple gates and can be functions of any size. Within this framework, we present necessary and sufficient conditions to identify all the possible functional expansions of a node that allow to eliminate a wire elsewhere in the network. These conditions are also given for the case of multiple variable expansion, providing an incremental mechanism to perform functional transformations involving any number of variables that can be applied in a very efficient manner. On the other hand, we will show in this paper that relevant simplifications can be obtained when this framework is applied to the particular case of AND-OR-NOT networks, resulting in important savings in the computational effort. When compared to previous approaches, the experimental results show an important reduction in the number of computations required.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
L. A. Entrena, K.-T. Cheng. "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal". IEEE Transactions on CAD, vol.14, n. 7, p. 909-916. 1995.
 
3
S.-C. Chang, K.-T. Cheng, N.-S. Woo, M. Marek-Sadowska. "Post-layout logic restructuring using alternative wires". IEEE Transactions on CAD, vol.16, n. 6, p. 587-596. June, 1997.
 
4
S. C. Chang, M. Marek-Sadowska, K.-T. Cheng. "Perturb and Simplify: Multilevel Boolean Network Optimizer". IEEE Transactions on CAD, vol. 15, no. 12, p. 1494-1504. November 1996.
 
5
 
6
 
7
B. Rohfleisch, F. Brglez. "Introduction of permissible bridges with application to logic optimization after technology mapping". Proc. European Design & Test Conference (ED&TC), p. 87-93. February 1994.
8
 
9
 
10
"SIS: A System for Sequential Circuit Synthesis" Report M92/41, University of California, Berkeley, May. 1992.


Collaborative Colleagues:
J. A. Espejo: colleagues
L. Entrena: colleagues
E. San Millán: colleagues
E. Oliás: colleagues