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High-level design for asynchronous logic
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 431 - 436  
Year of Publication: 2001
ISBN:0-7803-6634-4
Authors
Ross Smith  Theseus Logic
Michiel Ligthart  Theseus Logic
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Level Design flow for asynchronous circuits based on Register Transfer Level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
Berkel99
'Special issue on asynchronous circuits and systems' C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick, eds., Proceedings of the IEEE, 87(2), February 1999.
 
Brayton90
R. K. Brayton, G.D. Hachtel, and A.L. Sangiovanni-Vincentelli. Multilevel Logic Synthesis. Proceedings of the IEEE, Vol.78, No.2, February 1990, pp. 264-300
 
Fant96
 
Hauck95
Scott Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1): 69-93, January 1995.
 
Lsi95
LCB500K Preliminary Design Manual, LSI Logic Corporation, Milpitas, CA, 1995.
 
Nanya93
Takashi Nanya, 'Challenges to dependable asynchronous processor design', in Logic Synthesis and Optimization, Tsutomu Sasao, editor, Kluwer Academic Publishers, Dordrecht, The Netherlands, 1993.
 
Sia97
Semiconductor Industry Association, "The National Technology Road Map for Semiconductors', 1997 Edition
 
Sims58
C. Sims and H. J. Gray. Design criteria for autosynchronous circuits. Proc. Eastern Joint Computer Conf. (AFIPS), volume 14, pages 94-99, December 1958.
 
Sobelman98
Gerald E. Sobelman and Karl Fant. CMOS circuit design of threshold gates with hysteresis. Proc. International Symposium on Circuits and Systems, pages 61-64, June 1998.

Collaborative Colleagues:
Ross Smith: colleagues
Michiel Ligthart: colleagues