Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern

ABSTRACT

In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in reusable VLSI structure using EDA tool due to its regular structure. The main idea is to employ a time-multiplexed design scheme grouping the adjacent filter taps with correlated internal dataflow and with data transfer having same processing sequence between blocks. We simulated the proposed design scheme using SYNOPSYSTM and SPWTM. Index Terms - Decision feedback equalizer, QAM, reusable VLSI implementation, FIR filter.

REFERENCES

• 1: H. Samueli, "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FED Decoder", IEEE Journal of solid State Circuits, vol. 33, No. 12, Dec, 1998.
• 2: C. J. Nicole, et-al, "A Low-Power 128-Tap Digital Adaptive Equalizer for Broadband Modems", IEEE Journal of solid State Circuits, vol. 32, No. 11, Nov, 1997..
• 3: S. R. Meier, et-al, "Efficient and Reusable Time- Sharing Architectures for Equalizer Structure", in Proceeding of IEEE 2000 Custom Integrated Circuits Conference, pages 477-480, 2000.
• 4: H. Samueli, et-al "Design Techniques for Silicon Compiler Implementations of High-Speed FIR Digital Filters", IEEE JSSC, vol 31, May. 1996
• 5: S. Kinjo, et-al "A Design of FIR Filter Using CSD with Minimum Number of Registers", Proc. Of APCCS, 1996
• 6: S. C. Douglas, et-al "A pipelined LMS adaptive FIR filter architecture without adaptation delay", IEEE Transaction on Signal Processing, vol. 46, No. 3, Mar. 1998.
• 7: K. Azadet, C. J. Nicole, "Low-power equalizer architectures for high speed modems", IEEE Communications Magazine, vol. 36, Oct. 1998.
• 8: Simon Haykin, Adaptive filter theory (3rd ed.), Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 9: R. Jain, P.T. Yang, T. Yoshino, "FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits", IEEE Transactions on Signal Processing, vol. 39, issue: 7, Jul. 1991.
• 10: T.C. Denk, C.J. Nicol, P. Larsson, K. Azadet, "Reconfigurable hardware for efficient implementation of programmable FIR filters", Proc. of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, 1998, vol. 5
• 11: C--I HWANG and D. W. LIN, "Joint Low- Complexity Blind Equalization, Carrier Recovery and Timing Recovery with Application to Cable Modem Transmission", IEICE Trans. Commun. Vol. E82 B. No.1 Jan. 1999

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Performance, Theory