KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect

ABSTRACT

On-chip inductance extraction is difficult due to the global effect of inductance, and simulating the resulting dense partial inductance matrix is even more difficult. Furthermore, it is well known that simply discarding smallest terms to sparsify the inductance matrix can render the partial inductance matrix indefinite and result in an unstable circuit model. Recently a new circuit element, K , has been introduced to capture global effect of inductance by evaluating a corresponding sparse K matrix [1]. However, the reason that K has such local properties is not clear, and the positive semi-definiteness of the corresponding sparse K matrix is not proved. In this paper, we present the physical interpretation of K. Based on the physical interpretation, we explain why the faraway mutual K can be ignored (locality) and prove that after ignoring faraway mutual K ,the resultant K matrix is positive definite (stability). Together with a RKC equivalent circuit model, the locality and stability enables us to simulate RKC circuit directly and efficiently for real circuits. A new circuit simulation tool, KSim, has been developed by incorporating the new circuit element K into Berkeley SPICE. The RKC simulation matches better with the full partial inductance matrix simulation with significant less computing time and memory usage, compared to other proposed methods, such as shift-truncate method [2, 3].

REFERENCES

• 1: Anirudh Devgan , Hao Ji , Wayne Dai, How to efficiently capture on-chip inductance effects: introducing a new circuit element K, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 2: Byron Krauter , Lawrence T. Pileggi, Generating sparse partial inductance matrices with guaranteed stability, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.45-52, November 05-09, 1995, San Jose, California, United States
• 3: Zhijiang He , Mustafa Celik , Lawrence Pileggi, SPIE: sparse partial inductance extraction, Proceedings of the 34th annual conference on Design automation, p.137-140, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266050]
• 4: E. B. Rosa, "The self and mutual inductance of linear conductors," in Bulletin of the National Bureau of Standars, pp. 301-344, 1908.
• 5: A. E. Ruehli, "Inductance calculations in a complex integrated circuit environment," IBM Journal of Research and Development, pp. 470-481, Sept. 1972.
• 6: A. E. Ruehli, "Equivalent circuit models for three dimensional multiconductor systems," IEEE Trans. on MTT, pp. 216-220, Mar. 1974.
• 7: K. L. Shepard and Z. Tian, "Return-limited inductances: A practical approach to on-chip inductance extraction," in Proc. IEEE Custom Integrated Circuits Conference, pp. 453-456, 1999.
• 8: D. D. Ling and A. E. Ruehli, Circuit Analysis, Simulation and Design-Advances in CAD for VLSI. Netherlands: Elsevier Science Publishers B.V., 1987.
• 9: M. Kamon, M. J. Tsuk, and J. K. White, "FASTHENRY: A multipole-accelerated 3-D inductance extraction program," IEEE Trans. on MTT, pp. 216-220, Sept. 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  C. Computer Systems Organization

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.1 Numerical Algorithms and Problems
          Subjects: Computations on matrices

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Performance, Theory