A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability

ABSTRACT

This paper proposes a non-scan design-for-test-ability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.

REFERENCES

• 1: Hideo Fujiwara, Logic testing and design for testability, Massachusetts Institute of Technology, Cambridge, MA, 1985
• 2: Peter C. Maxwell , Robert C. Aitken , Vic Johansen , Inshen Chiang, The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.358-364, October 26-30, 1991
• 3: Satoshi Ohtake , Hiroki Wada , Toshimitsu Masuzawa , Hideo Fujiwara, A non-scan DFT method at register-transfer level to achieve complete fault efficiency, Proceedings of the 2000 conference on Asia South Pacific design automation, p.599-604, January 2000, Yokohama, Japan [doi>10.1145/368434.368825]
• 4: Satoshi Ohtake , Toshimitsu Masuzawa , Hideo Fujiwara, A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency, Proceedings of the 7th Asian Test Symposium, p.204, December 02-04, 1998
• 5: Hiroki Wada , Toshimitsu Masuzawa , Kewal K. Saluja , Hideo Fujiwara, Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency, Proceedings of the 13th International Conference on VLSI Design, p.300, January 04-07, 2000
• 6: B. T. Murray and J. P. Hayes: "Hierarchical test generation using pre computed tests for modules," IEEE Trans. on CAD, Vol. 9, No. 6, pp. 594-603, June 1990.
• 7: S. Ohtake, S. Nagai, H. Wada, and H. Fujiwara: "A non-scan DFT method at RTL based on fixed-control testability to achieve 100% fault efficiency," Technical report, Information Science Technical Report: TR2000009 (http://isw3.aist-nara.ac.jp/IS/TechReport2/report/2000009.ps), Nara Institute of Science and Technology, 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

Additional Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.2 Input/Output Devices
          Subjects: Channels and controllers

  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Performance, Theory, Verification