Trace-driven system-level power evaluation of system-on-a-chip peripheral cores

ABSTRACT

Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, measuring gate-level power consumption per instruction, and then annotating a system-level simulation model with the obtained data. In this work, we describe a method for speeding up the evaluation further, through the use of instruction traces and trace simulators for every core, not just microprocessor cores. Our method shows noticeable speedups at an acceptable loss of accuracy. We show that reducing trace sizes can speed up the method even further. The speedups allow for more extensive system-level power exploration and hence better optimization.

REFERENCES

• 1: M. Barocci, L. Benini, A. Bogliolo, B. Ricco, G. De Micheli. Lookup Table Power Macro-Models for Behavioral Library Components. Design Automation and Test In Europe, March 1998.
• 2: R. J. Evans, P.D. Franzon. Energy Consumption Modeling and Optimization for SRAMs, IEEE Journal of Solid-State Circuits, Vol. 30, No. 5, pp. 571-579, 1995.
• 3: Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
• 4: Tony Givargis , Frank Vahid , Jörg Henkel, A hybrid approach for core-based system-level power modeling, Proceedings of the 2000 conference on Asia South Pacific design automation, p.141-146, January 2000, Yokohama, Japan [doi>10.1145/368434.368593]
• 5: Subodh Gupta , Farid N. Najm, Power macromodeling for high level power estimation, Proceedings of the 34th annual conference on Design automation, p.365-370, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266171]
• 6: Cheng-Ta Hsieh , Massoud Pedram , Gaurav Mehta , Fred Rastgar, Profile-driven program synthesis for evaluation of system power dissipation, Proceedings of the 34th annual conference on Design automation, p.576-581, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266288]
• 7: S.M. Kang. Accurate Simulation of Power Dissipation in VLSI Circuits. IEEE Journal of Solid-State Circuits, vol. CS21, no. 5, pp. 889-891, October 1986.
• 8: Thomas H. Krodel, PowerPlay-Fast Dynamic Power Estimation Based on Logic Simulation, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.96-100, October 14-16, 1991
• 9: Marcello Lajolo , Luciano Lavagno , Anand Raghunathan , Sujit Dey , Alberto Sangiovanni-Vincentelli, Efficient Power Estimation Techniques for HW/SW Systems, Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design, p.191, March 04-05, 1999
• 10: Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
• 11: Yanbing Li , Jörg Henkel, A framework for estimation and minimizing energy dissipation of embedded HW/SW systems, Proceedings of the 35th annual conference on Design automation, p.188-193, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277097]
• 12: E. Macii, M. Pedram. High-Level Power Modeling, Estimation, and Optimization. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 17, no. 11, November 1998.
• 13: D. Marculescu, R. Marculescu, M. Pedram. Information Theoretic Measures for Power Analysis. IEEE Transactions on Computer Aided Design, vol. 15, no. 6, pp. 599-610, 1996.
• 14: Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin, Energy characterization based on clustering, Proceedings of the 33rd annual conference on Design automation, p.702-707, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240651]
• 15: M. Nemani, F. Najm. Toward a High Level Power Estimation Capability. IEEE Transactions on Computer Aided Design, vol. 15, no. 6, pp. 588-598, 1996.
• 16: Tajana Šimunić , Luca Benini , Giovanni De Micheli, Cycle-accurate simulation of energy consumption in embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.867-872, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310090]
• 17: Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
• 18: R. Tjarnstorm. Power Dissipation Estimate by Switch Level Simulation. IEEE symposium on Circuits and Systems, pp. 881-884, 1989.
• 19: Frank Vahid , Tony Givargis, Incorporating cores into system-level specification, Proceedings of the 11th international symposium on System synthesis, p.43-48, December 02-04, 1998, Hsinchu, Taiwan, China
• 20: Virtual Socket Interface Association, Architecture Document, http://www.vsi.org, 1997.
• 21: G.Y Yacoub, W.H. Ku. An Accurate Simulation Technique for Short-Circuit Power Dissipation Based on Current Component Isolation. IEEE International Symposium on Circuits and Systems, pp. 1157-1161, 1989.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory

Keywords:
cores, intellectual property, low power system design, parameterized architectures, system-level modeling, system-on-a-chip