Low power design challenges for the decade (invited talk)

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Low power design challenges for the decade (invited talk)

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 293 - 296

Year of Publication: 2001

ISBN:0-7803-6634-4

Author

Shekhar Borkar

Microprocessor Research Labs, Intel Corp., Hillsboro, OR

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 80, Citation Count: 16

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Technology scaling will become difficult beyond 0.18 micron. For continued growth in performance, transistor density, and reduced energy per computation, circuit design will have to employ a new set of design techniques, with adequate design automation tools support. This paper discusses a few such techniques that reduce active and leakage power, and deliver higher performance. It concludes by pointing out some of the potential paradigm shifts.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
	2	Intel SpeedStep-technology, http://www.intel.com.
	3	D. Ditzel, "Transmeta's Crusoe," Proceedings of COOL Chips III conference, Tokyo, Japan, April 24-25, 2000.
	4	Y. Ye, S. Borkar, V. De, "A New Technique for Standby Leakage Reduction in High-Performance Circuits," 1998 Symposium on VLSI Circuits, June 1998.
	5	Anantha P. Chandrakasan , William J. Bowhill , Frank Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press, 2000
	6	Fred J. Pollack, New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only), Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.2, November 16-18, 1999, Haifa, Israel

CITED BY 16

	Volkan Kursun , Eby G. Friedman, Low swing dual threshold voltage domino logic, Proceedings of the 12th ACM Great Lakes symposium on VLSI, April 18-19, 2002, New York, New York, USA
	Volkan Kursun , Siva G. Narendra , Vivek K. De , Eby G. Friedman, Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.514-522, June 2003
	Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002
	Yu-Hui Huang , Po-Yuan Chen , TingTing Hwang, Switching-activity driven gate sizing and Vth assignment for low power design, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Vishak Venkatraman , Atul Maheshwari , Wayne Burleson, Mitigating static power in current-sensed interconnects, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Tsuang-Wei Chang , Ting-Ting Hwang , Sheng-Yu Hsu, Functionality directed clustering for low power MTCMOS design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Yi-Ping You , Chun-Yen Tseng , Yu-Hui Huang , Po-Chiun Huang , TingTing Hwang , Sheng-Yu Hsu, Low-power techniques for network security processors, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	M. Müller , S. Simon , H. Gryska , A. Wortmann , S. Buch, Low power synthesizable register files for processor and IP cores, Integration, the VLSI Journal, v.39 n.2, p.131-155, March 2006
	Gian Luca Loi , Banit Agrawal , Navin Srivastava , Sheng-Chih Lin , Timothy Sherwood , Kaustav Banerjee, A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Zhiyu Liu , Volkan Kursun, Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages, Proceedings of the 7th International Symposium on Quality Electronic Design, p.31-36, March 27-29, 2006
	Nevin Kirman , Meyrem Kirman , Rajeev K. Dokania , Jose F. Martinez , Alyssa B. Apsel , Matthew A. Watkins , David H. Albonesi, Leveraging Optical Technology in Future Bus-based Chip Multiprocessors, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.492-503, December 09-13, 2006
	Takashi Kawanami , Masakazu Hioki , Yohei Matsumoto , Toshiyuki Tsutsumi , Tadashi Nakagawa , Toshihiro Sekigawa , Hanpei Koike, Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA, IEICE - Transactions on Information and Systems, v.E90-D n.12, p.1947-1955, December 2007
	Ang-Chih Hsieh , Tzu-Teng Lin , Tsuang-Wei Chang , Tingting Hwang, A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-25, August 2007
	Mingoo Seok , Dennis Sylvester , David Blaauw, Optimal technology selection for minimizing energy and variability in low voltage applications, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Hiroshi Shinohara , Hideaki Monji , Masahiro Iida , Toshinori Sueyoshi, A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices, IEICE - Transactions on Information and Systems, v.E90-D n.12, p.1986-1989, December 2007
	Wanping Zhang , Wenjian Yu , Xiang Hu , Amirali Shayan , A. Ege Engin , Chung-Kuan Cheng, Predicting the worst-case voltage violation in a 3D power network, Proceedings of the 11th international workshop on System level interconnect prediction, July 26-27, 2009, San Francisco, CA, USA