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Equivalence checking of integer multipliers
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 169 - 174  
Year of Publication: 2001
ISBN:0-7803-6634-4
Authors
Jiunn-Chern Chen  Department of Computer & Information Science, National Chiao Tung University, Hsinchu, Taiwan 300, R. O. C.
Yirng-An Chen
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we address on equivalence checking of integer multipliers, especially for the multipliers without structure similarity. Our approach is based on Hamaguchi's backward substitution method with the following improvements: (1) automatic identification of components to form proper cut points and thus dramatically improve the backward substitution process, (2) a layered-backward substitution algorithm to reduce the number of substitutions, and (3) Multiplicative Power Hybrid Decision Diagrams(*PHDDs) as our word-level representation rather than *BMD in Hamaguchi's approach. Experimental results show that our approach can efficiently check the equivalence of two integer multipliers. To verify the equivalence of a 32 x 32 array multiplier versus a 32 x 32 Wallace tree multiplier, our approach takes about 57 CPU seconds using 11 Mbytes, while Stanion's approach took 21027 seconds using 130 MBytes. We also show that the complexity of our approach grows cubically O(n3).


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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A. D. Booth. A signed binary multiplication technique. In Journal of Mechanics and Applied Mathematics, pages 236-240, 1951.
 
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B. Yang, Y.-A. Chen, R. E. Bryant, and D. R. O'Hallaron. Space- and time-efficient bdd construction via working set control. In Proceedings of ASP-DAC '98, pages 423-432, Yokohoma, Japan, Feb. 1998.


Collaborative Colleagues:
Jiunn-Chern Chen: colleagues
Yirng-An Chen: colleagues