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A construction of minimal delay Steiner tree using two-pole delay model
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 126 - 132  
Year of Publication: 2001
ISBN:0-7803-6634-4
Authors
LiYi Lin  Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043
YiYu Liu  Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043
Ting Ting Hwang  Department of Computer Science, National Tsing Hua University, HsinChu, Taiwan 30043
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
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ABSTRACT

In this paper, we will study the construction of a Steiner routing tree for a given net with the objective of minimizing the delay of the routing tree. Previous researches adopt Elmore delay model to compute delay. However, with the advancement of IC technology, a more accurate delay model is required. Therefore, in this paper, we will use two-pole delay model to compute the cost function of a Steiner tree. Moreover, we propose a new algorithm to construct the Steiner tree. Our algorithm takes into consideration the net topology, the total wire length and the longest path from the source to sink. Experimental results show that our algorithm is very effective and efficient as compared to [8].


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Collaborative Colleagues:
LiYi Lin: colleagues
YiYu Liu: colleagues
Ting Ting Hwang: colleagues