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ABSTRACT
In this paper, we will study the construction of a Steiner routing tree for a given net with the objective of minimizing the delay of the routing tree. Previous researches adopt Elmore delay model to compute delay. However, with the advancement of IC technology, a more accurate delay model is required. Therefore, in this paper, we will use two-pole delay model to compute the cost function of a Steiner tree. Moreover, we propose a new algorithm to construct the Steiner tree. Our algorithm takes into consideration the net topology, the total wire length and the longest path from the source to sink. Experimental results show that our algorithm is very effective and efficient as compared to [8].
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/196244.196428]
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A. B. Kahng, S. Muddu, "Two-pole Analysis of Interconnection Trees", IEEE MCMC Conf., pp.105-110, 1995.
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Youxin Gao, D. F. Wong, "Wire-Sizing Optimization with Induztance Consideration Using Transmission-Line Model", IEEE Trans. CAD, vol. 18, no. 12, pp. 1759-1767, 1999.
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16
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H. Hou, J. Hu, S. S. Sapatnekar, "Non-Hanan Routing", IEEE Trans. CAD, vol. 18, no. 4, pp. 436-444, 1999.
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18
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A. B. Kahng, G. Robins, "On Optimal Interconnections for VLSI", Kluwer Academic Publishers, Boston, MA, 1995.
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