Reducing bus delay in submicron technology using coding

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Reducing bus delay in submicron technology using coding

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2001 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 109 - 114

Year of Publication: 2001

ISBN:0-7803-6634-4

Authors

Paul P. Sotiriadis	Department of EECS, Massachusetts Inst. of Technology, Cambridge, MA
Anantha Chandrakasan	Department of EECS, Massachusetts Inst. of Technology, Cambridge, MA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IPSJ : Information Processing Society of Japan
IEEE HK CAS : IEEE HK CAS and Comm. Joint Chapter
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 15

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ABSTRACT

In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 15

	Srinivasa R. Sridhara , Naresh R. Shanbhag, A low-power bus design using joint repeater insertion and coding, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Brock J. LaMeres , Kanupriya Gulati , Sunil P. Khatri, Controlling inductive cross-talk and power in off-chip buses using CODECs, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	K. Najeeb , Vishal Gupta , V. Kamakoti, Delay and peak power minimization for on-chip buses using temporal redundancy, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Wen-Wen Hsieh , Po-Yuan Chen , TingTing Hwang, A bus architecture for crosstalk elimination in high performance processor design, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Chittarsu Raghunandan , K. S. Sainarayanan , M. B. Srinivas, Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Nallamothu Satyanarayana , Madhu Mutyam , A Vinaya Babu, Exploiting on-chip data behavior for delay minimization, Proceedings of the 2007 international workshop on System level interconnect prediction, March 17-18, 2007, Austin, Texas, USA
	Chunjie Duan , Sunil P. Khatri, Exploiting Crosstalk to Speed up On-Chip Buses, Proceedings of the conference on Design, automation and test in Europe, p.20778, February 16-20, 2004
	Lin Li , N. Vijaykrishnan , Mahmut Kandemir , Mary Jane Irwin, A Crosstalk Aware Interconnect with Variable Cycle Transmission, Proceedings of the conference on Design, automation and test in Europe, p.10102, February 16-20, 2004
	Madhu Mutyam, Selective shielding: a crosstalk-free bus encoding technique, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	K. S. Sainarayanan , Chittarsu Raghunandan , M. B. Srinivas, Bus encoding schemes for minimizing delay in VLSI interconnects, Proceedings of the 20th annual conference on Integrated circuits and systems design, September 03-06, 2007, Copacabana, Rio de Janeiro
	Madan Arvind , Bharadwaj Amrutur, Power reduction in on-chip interconnection network by serialization, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Rohit Singhal , Gwan Choi , Rabi N. Mahapatra, Data handling limits of on-chip interconnects, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.707-713, June 2008
	Jingyi Zhang , Qing Wu , Qinru Qiu, Bus encoding for simultaneous delay and energy optimization, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Basel Halak , Alex Yakovlev, Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Madhu Mutyam, Selective shielding technique to eliminate crosstalk transitions, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.14 n.3, p.1-20, May 2009