| Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead |
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International Symposium on Physical Design
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Proceedings of the 2001 international symposium on Physical design
table of contents
Sonoma, California, United States
Pages: 100 - 105
Year of Publication: 2001
ISBN:1-58113-347-2
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Author
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Wai-Kei Mak
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Department of Computer Science and Engineering, University of South Florida, 4202 E. Fowler Avenue, ENB 118, Tampa, Florida
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Downloads (6 Weeks): 3, Downloads (12 Months): 11, Citation Count: 0
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ABSTRACT
Logic replication is known to be an effective technique to reduce the number of cut nets in partitioned circuits. A new replication model calledfunctional replicationis particularly useful for partitioning technology mapped circuits [7]. Functional replication differs from traditional replication because it considers the functional dependency of the different output signals of a logic cell on its input signals. Functional replication can lead to a higher reduction in the number of cut nets than traditional replication. In this paper, we give the first theoretical treatment of the min-cut partitioning problem with functional replication. We present a novel two-phase algorithm to compute a min-cut bipartition of a technology mapped circuit with functional replication using minimum amount of area overhead. And we show that our algorithm can be applied to improve the solution produced by any area-constrained functional replication partitioning heuristic.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Partitioning93 benchmark. available at http://www.cbl.ncsu.edu/CBL Docs/partn93.html.
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M. Enos, S. Hauck, and M. Sarrafzadeh. Evaluation and optimization of replication algorithms for logic bipartitioning. IEEE Transactions on CAD, 18(9):1237-1248, September 1999.
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3
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4
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J. Hwang and A. El Gamal. Min-cut replication in partitioned networks. IEEE Transactions on CAD, 14(1):96-106, January 1995.
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5
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S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, pages 671-680, May 1983.
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6
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C. Kring and A. R. Newton. A cell-replicating approach to mincut-based circuit partitioning. In Proceedings of IEEE Int'l Conf. on Computer-Aided Design, pages 2-5, 1991.
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Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States
[doi> 10.1145/196244.196364]
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L. T. Liu, M. T. Kuo, C. K. Cheng, and T. C. Hu. A replication cut for two-way partitioning. IEEE Transactions on CAD, 14(5):623-630, May 1995.
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W. K. Mak and D. F. Wong. Minimum replication min-cut partitioning. IEEE Transactions on CAD, 16(10):1221-1227, October 1997.
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Xilinx Inc. The Programmable Logic Data Book, 1996.
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12
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