Multi-GHz interconnect effects in microprocessors

ABSTRACT

High frequency on-chip interconnect examples are accurately analyzed using full-wave PEEC (Partial Element Equivalent Circuit) analysis. All wire currents and voltages (or delays) are visualized using 3D animations to aid intuitive understanding of new, high frequency interconnect effects.

REFERENCES

• 1: A. Deutsch, G. V. Kopcsay, P. Restle, et al, "When are Transmission-Line Effects Important for On Chip Interconnections?" IEEE Trans. Microwave Theory Tech. (USA) Vol. 45, No. 10, pt. 2, pp. 1836-46, Oct. 1997.
• 2: P. J. Restle, K. A. Jenkins, A. Deutsch and P. W. Cook, "Measurement and Modeling of On-Chip Transmission-Line Effects in a 400 MHz Microprocessor," IEEE Journal of Solid- State Circuits, Vol. 33 No. 4, pp. 662-665, Apr. 1998.
• 3: Phillip Restle , Albert Ruehli , Steven G. Walker, Dealing with inductance in high-speed chip design, Proceedings of the 36th ACM/IEEE conference on Design automation, p.904-909, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.310096]
• 4: P. J. Restle, A. E. Ruehli, S. G. Walker, G. Papadopoulos, "Full-Wave PEEC Time-Domain Method for the Modeling of On-Chip Interconnects," IEEE Trans. on Computer-Aided Design, (in press).
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• 8: C. Anderson et al, "Physical Design of a Fourth-Generation POWER GHz Microprocessor," IEEE ISSCC Tech. Dig. pp. 232-233, Feb. 2001.

INDEX TERMS

General Terms:
Design

Keywords:
circuit-tuning, clock distribution, extraction, full-wave analysis, inductance, interconnect, simulation