ACM Home Page
Please provide us with feedback. Feedback
Reporting of standard cell placement results
Full text PdfPdf (72 KB)
Source International Symposium on Physical Design archive
Proceedings of the 2001 international symposium on Physical design table of contents
Sonoma, California, United States
Pages: 30 - 35  
Year of Publication: 2001
ISBN:1-58113-347-2
Author
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 10,   Downloads (12 Months): 20,   Citation Count: 4
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/369691.369727
What is a DOI?

ABSTRACT

VLSI fabrication technology has advanced rapidly, bringing with it a strong demand for faster and better design automation tools. Accurate reporting of results for placement approaches is crucial to the development of improved automation tools; unfortunately, publicly available placement benchmarks are outdated, and there are wide variations in their interpretation.At best, poor benchmarks and differences in interpretation result in misunderstandings of the effectiveness of some approaches. At worst, they can motivate research in areas of very little promise, while other areas which have true potential are ignored. In this paper, we describe current standard cell placement benchmarks and illustrate common differences in their interpretation, in the hope that a clear understanding of these issues will allow research to be directed and evaluated more efficiently.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
2
3
 
4
5
 
6
W. C. Elmore. The transient response of damped linear networks with particular. Journal of Applied Physics, 19(1):55-63, January 1948.
 
7
 
8
GSRC. Bookshelf slot. http://www.gigascale.org/bookshelf.
 
9
Takeo Hamada, Chung-Kuan Cheng, and Paul M. Chau. An efficient multilevel placement technique using hierarchical partitioning. IEEE Trans. on Circuits and Systems, 39(6):432-439, June 1992.
10
 
11
 
12
InternetCAD Inc. Benchmark results at http://www.internetcad.com. Results compare with TimberWolf 7.0.
 
13
J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich. Gordian: Vlsi placement by quadratic programming and slicing optimization. IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems, 10(3):356-365, 1991.
14
15
16
 
17
L. T. Pillage and R. A. Rohrer. Asymptotic waveform evaluation for timing analysis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 9(4):352-366, April 1990.
 
18
 
19
W.-J. Sun and C. Sechen. Efficient and effective placement for very large circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems, 14(3):349-359, 1995.
20
 
21
 
22
Yeong-Yil Yang and Chong-Min Kyung. HALO: An efficient global placement strategy for standard cels. IEEE Trans. on Computer-Aided Design of Integrated Circuits andSystems, page 1024, 1992.
23
 
24