Performance analysis using the MIPS R10000 performance counters

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Performance analysis using the MIPS R10000 performance counters

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Conference on High Performance Networking and Computing archive
Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) table of contents

Pittsburgh, Pennsylvania, United States

Article No. 16

Year of Publication: 1996

ISBN:0-89791-854-1

Authors

Marco Zagha	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA
Brond Larson	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA
Steve Turner	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA
Marty Itzkowitz	Silicon Graphics Inc., 2011 N. Shoreline Blvd., Mountain View, CA

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 9, Downloads (12 Months): 50, Citation Count: 54

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Tuning supercomputer application performance often requires analyzing the interaction of the application and the underlying architecture. In this paper, we describe support in the MIPS R10000 for non-intrusively monitoring a variety of processor events -- support that is particularly useful for characterizing the dynamic behavior of multi-level memory hierarchies, hardware-based cache coherence, and speculative execution. We first explain how performance data is collected using an integrated set of hardware mechanisms, operating system abstractions, and performance tools. We then describe several examples drawn from scientific applications that illustrate how the counters and profiling tools provide information that helps developers analyze and tune applications.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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