ACM Home Page
Please provide us with feedback. Feedback
Pre-layout prediction of interconnect manufacturability
Full text PdfPdf (229 KB)
Source International Workshop on System-Level Interconnect Prediction archive
Proceedings of the 2001 international workshop on System-level interconnect prediction table of contents
Sonoma, California, United States
Pages: 167 - 173  
Year of Publication: 2001
ISBN:1-58113-315-4
Authors
Phillip Christie  Philips Research Labs., Eindhoven, The Netherlands
José Pineda de Gyvez  Philips Research Labs., Eindhoven, The Netherlands
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 14,   Citation Count: 6
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/368640.368826
What is a DOI?

ABSTRACT

Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
W. E. Donath, "Statistical properties of the placement of a graph," SIAM J. Applied Mathematics, vol. 16, no. 2, pp. 439-457, 1968.
 
2
B. S. Landman and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs," IEEE Trans. Computers, vol. 20, pp. 1469, 1971.
 
3
W. E. Donath, "On the equivalence of memory to random logic," IBM J. Res. Dev, vol. 18, pp. 401-407, 1974.
 
4
W. R. Heller, W. F. Mikhail, and W. E. Donath, "Prediction of wiring space requirements for LSI," Design Automat. Fault-Tolerant Comput., pp. 117-144, 1978.
 
5
M. Feuer, "Connectivity of random logic," IEEE Trans. Computers, vol. C-31, pp. 29-33, 1982.
 
6
W. R. Heller, C. G. Hsi, and W. F. Mikhaill, "Wirability|designing wiring space for chips and chip packages," IEEE Design and Test Magazine, pp. 43-51, AUGUST 1984.
 
7
T. Chiba, 'Impact of the LSI on high-speed computer packaging," IEEE Trans. Computers, vol. C-27, pp. 319-325, 1978.
 
8
W.E. Donath, "Placements and average interconnection lengths of computer logic," IEEE Trans. Circuits and Systems, vol. CAS-26, no. 4, pp. 272-277, 1979.
 
9
N. Harada, "LSI interconnect length prediction method using statistical mechanical placements theory," NEC Research and Development Journal, vol. 72, pp. 56-63, January 1984.
 
10
Wilm Donath, "Wire length distribution for placements of computer logic," IBM J. Res. Develop., vol. 25, no. 3, pp. 152-155, May 1981.
 
11
D. K. Ferry, 'Interconnection lengths and VLSI," IEEE Circuits and Devices Magazine, pp. 39-42, July 1985.
 
12
H. B. Bakoglu and J. D. Meindl, "A system level circuit model for multi- and single chip cpus," in IEEE International Solid State Circuits Conference (ISSCC `87), 1987, pp. 308-309. Nether-
 
13
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, 1990.
 
14
J. Davis and J. D. Meindl, "Optimal low power interconnect networks," in Proc. IEEE Symposium on VLSI Technology, 1996, pp. 78-79.
 
15
J. A. Davis, V. De, and J. D. Meindl, "A stochastic wire-length distribution for gigascale integration (GSI)|part II: Applications to clock frequency, power dissipation, and chip size estimation," IEEE Trans. Electron Devices, vol. 45, no. 3, pp. 591-597, March 1998.
16
17
 
18
T. N. Theis, "The future of interconnection technology," IBM J. Research and Development, vol. 44, no. 3, pp. 379-390, 2000.
 
19
G. A. Sai-Halasz, "Performance trends in high-end processors," Proc. IEEE, vol. 83, pp. 18, 1995.
20
 
21
P. Chong and R. K. Brayton, "Estimating and optimizing routing utilization in dsm design," in Proc. 1st International Workshop on System Level Interconnect Prediction. March 1999, pp. 97-102, ACM.
 
22
I. Chen and A.J. Strojwas, "Rye: Realistic yield simulator for VLSI structural failures," in Proc. IEEE Int. Test Conference, 1987, pp. 31-42.
 
23
D. M. H. Walker, Yield Simulation for Integrated Circuits, Kluwer, Boston MA, 1987.
 
24
P. Schvan, D.Y. Montuno, and R. Hadaway, Defect and Fault Tolerance in VLSI Systems, vol. 1, pp. 117-127, Plenum, New York, 1989.
 
25
J. Pineda de Gyvez and C. Di, "IC defect sensitivity for footprint-type defects," IEEE Trans. on Computer-Aided Design, vol. 11, pp. 638-658, May 1992.
 
26
 
27
 
28
S.Y. Kuo, "Yor: A yield optimizing routing algorithm by minimizing critical areas and vias," IEEE Trans. on Computer Aided Design, vol. 12, pp. 1303-1311, September 1993.
 
29
E.P. Huijbregts, H.Xue, and J.A.G. Jess, "Routing for reliable manufacturing," IEEE Trans. on Semiconductor Manufacturing, vol. 8, pp. 188-194, May 1995.
 
30
V. K. R. Chilivuri and I. Koren, "Layout synthesis techniques for yield enhancement," IEEE Trans. on Semiconductor Manufacturing, vol. 8, pp. 178-187, May 1995.
31
 
32
 
33
 
34
 
35
 
36
Phillip Christie, "A differential equation for placement analysis," Submitted to IEEE Trans. on VLSI Systems, 2000.

CITED BY  6

Collaborative Colleagues:
Phillip Christie: colleagues
José Pineda de Gyvez: colleagues