Yield modeling and BEOL fundamentals

ABSTRACT

The advent of deep submicron technologies with larger die sizes lends itself to an increase in fabrication cost. An appropriate yield forecast renders significant benefits in both time-to-market and manufacturing cost prediction. Yield forecasting is essential for the development of new products as it effectively shows if a design is feasible of meeting its cost objectives or not. In mature manufacturing processes, spot defects are the main detractors in the successful outcome of an IC. Their manifestation is as local disturbances of silicon layer structures. Spot defects are in essence random phenomena occurring on the wafer with certain stochastic size, spatial distribution, and frequency of occurrence per unit area. To verify the robustness of an IC it is necessary to extract its “critical areas”. The so-called critical areas are the places in the layout where defects can induce and IC faulty behavior such as a short or a break circuit. A figure of merit that measures the layouts robustness is obtained as the ratio of the total critical area to the layout area. This figure of merit is known as defect sensitivity. Knowledge of the designs defect sensitivity and the stochastic behavior of defects in the manufacturing line is used to ultimately predict yield.This tutorial reviews the basics on spot defect modeling, critical area modeling and its application in interconnect yield analysis.

REFERENCES

• 1: TI Photolithography expert system for improved estimation of IC critical area. AU Chia-M-P-C; Allan-G-A; Walton-A-J. SO Microelectronic Manufacturing Yield, Reliability, and Failure Analysis IV, Santa Clara, CA, USA, 23-24 Sept. 1998. In:Proceedings-of-the-SPIE-The-International-Society-for-Optical- Engineering (USA), vol.3510, p.74-81, 1998.
• 2: TI A comparison of critical area analysis tools IC yield. AU Fitzpatrick-S; O-Donoghue-G; Cheek-G. SO IEEE/SEMI. 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, Boston, MA, USA, 23-25 Sept. 1998. In: p.31-3, 1998.
• 3: TI Critical area computation via Voronoi diagrams. AU Papadopoulou-E; Lee-D-T. SO IEEE-Transactions-on-Computer-Aided-Design-of-Integrated-Circuits-and-Systems (USA), vol.18, no.4, p.463-74, April 1999.
• 4: Gerard A. Allan, A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation, Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.44, November 02-04, 1998
• 5: TI Yield modeling based on in-line scanner defect sizing and a circuit's critical area. AU Milor-L-S. SO 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 97 Proceedings, Cambridge, MA, USA, 10-12 Sept. 1997. In: IEEE-Transactions-on-Semiconductor-Manufacturing (USA), vol.12, no.1, p.26-35, Feb. 1999.
• 6: TI Critical area extraction for soft fault estimation. AU Allan-G-A; Walton-A-J. SO IEEE-Transactions-on-Semiconductor-Manufacturing (USA), vol.11, no.1, p.146-54, Feb. 1998. , Published: IEEE.
• 7: F. M. Gonçalves , Isabel Teixeira , João Paulo Teixeira, Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems, 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems, p.29-37, October 20-22, 1997
• 8: Gerard A. Allan , Anthony J. Walton, Efficient critical area estimation for arbitrary defect shapes, 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems, p.20-28, October 20-22, 1997
• 9: TI Efficient critical area measurements of IC layout applied to quality and reliability enhancement. AU Allan-G-A; Walton-A-J. SO Microelectronics-and-Reliability (UK), vol.37, no.12, p.1825-33, Dec. 1997. , Published: Elsevier.
• 10: Frederic Duvivier , Gerard A. Allan, Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing Environment, Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems, p.48, November 06-08, 1996
• 11: TI Improved critical area prediction by application of pattern recognition techniques. AU Mattick-J-H-N; Kelsall-R-W; Miles-R-E. SO 7th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Enschede, Netherlands, 8-11 Oct. 1996. In:Microelectronics-and-Reliability (UK), vol.36, no.11-12, p.1815-18, Nov.-Dec. 1996.
• 12: TI ULSI design-for-manufacturability: a yield enhancement approach. AU Tyagi-A; Bayoumi-M-A; Ed. by Ambler-T; Abadir-M. SO Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing, Austin, TX, USA, 16-17 May 1994. In: p.80-9, 1996.
• 13: Zhan Chen , I. Koren, Layer assignment for yield enhancement, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.173, November 13-15, 1995
• 14: G. A. Allan , A. J. Walton, Hierarchical critical area extraction with the EYE tool, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.28, November 13-15, 1995
• 15: P. K. Nag , W. Maly, Hierarchical extraction of critical area for shorts in very large ICs, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.19, November 13-15, 1995
• 16: I. Bubel , W. Maly , T. Waas , P. K. Nag , H. Hartmann , D. Schmitt-Landsiedel , S. Griep, AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.10, November 13-15, 1995
• 17: Hua Xue , Chennian Di , J. A. G. Jess, A net-oriented method for realistic fault analysis, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.78-83, November 07-11, 1993, Santa Clara, California, United States
• 18: TI An interactive VLSI CAD tool for yield estimation. AU Wagner-I-A; Koren-I. SO IEEE-Transactions-on-Semiconductor-Manufacturing (USA), vol.8, no.2, p.130-8, May 1995.
• 19: Hua Xue , Chennian Di , Jochen A. G. Jess, Fast Multi-Layer Critical Area Computation, Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p.117-124, October 27-29, 1993
• 20: TI Algorithm for extracting integrated circuit critical areas associated with point defects. AU Stamenkovic-Z. SO International-Journal-of-Electronics (UK), vol.77, no.3, p.369-76, Sept. 1994.
• 21: TI Fault probabilities in routing channels of VLSI standard cell designs. AU Spiegel-G. SO Proceedings of IEEE VLSI Test Symposium, Cherry Hill, NJ, USA, 25-28 April 1994.
• 22: TI Yield enhancement in the routing phase of integrated circuit layout synthesis. AU Tyagi-A; Bayoumi-M; Manthravadi-P; Ed. by Lea-R-M; Tewksbury-S. SO Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI), San Francisco, CA, USA, 19-21 Jan. 1994. In: p.52-60, 1994.
• 23: TI YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias. AU Kuo-S-Y. SO IEEE-Transactions-on-Computer-Aided-Design-of-Integrated-Circuits-and-Systems (USA), vol.12, no.9, p.1303-11, Sept. 1993. p.507-8.
• 24: TI A layout-driven yield predictor and fault generator for VLSI. AU Dalal-A-R; Franzon-P-D; Lorenzetti-M-J. SO IEEE-Transactions-on-Semiconductor-Manufacturing (USA), vol.6, no.1, p.77-82, Feb. 1993.
• 25: TI YOR: a yield optimizing routing algorithm by minimizing critical area and vias. AU Sy-Yen-Kuo. SO Proceedings. The European Conference on Design Automation, Brussels, Belgium, 16-19 March 1992, p.525-9.
• 26: TI Critical area analysis. AU Walker-D-M-H; Ed. by Jain-V-K; Wyatt-P-W. SO Proceedings. International Conference on Wafer Scale Integration (Cat.No.92CH3088-2), San Francisco, CA, USA, 22-24 Jan. 1992, p.281-90. Sponsors: IEEE.
• 27: A. Pitaksanonkul , S. Thanawastien , C. Lursinsap , J. A. Gandhi, DTR: a defect-tolerant routing algorithm, Proceedings of the 26th ACM/IEEE conference on Design automation, p.795-798, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74532]
• 28: TI VLASIC: a yield simulator for integrated circuits. AU Walker-H; Director-S-W. SO IEEE International Conference on Computer-Aided Design: ICCAD-85. Digest of Technical Papers (Cat. No.85CH2233-5), Santa Clara, CA, USA, 18-21 Nov. 1985, p.318-20.
• 29: TI Realistic yield simulation for VLSIC structural failures. AU Chen-I; Strojwas-A-J. SO International Conference on Computer-Aided Design of Integrated Circuits, Santa Clara, CA, USA, 11-13 Nov. 1986.
• 30: TI Realistic yield simulation for IC structural failures. AU Chen-I; Strojwas-A-J SO IEEE International Conference on Computer-Aided Design: ICCAD-86. A Conference for the EE CAD Professional. Digest of Technical Papers (Cat. No.86CH2353-1), Santa Clara, CA, USA, 11-13 Nov. 1986, p.220- 3. Published: IEEE Comput. Soc. Press, Washington, DC, USA, 1986, xxxii +523 pp
• 31: TI CALYPSO-Critical Area, Lifetime, and Yield Predicting Software. AU Miskowiec-P; Kunze-D; Lukat-K. SO ESREF 2000. 11th European Symposium on the Reliability of Electron Devices, Dresden, Germany, 2-6 Oct. 2000. In:Microelectronics-Reliability (UK), vol.40, no.8-10, p.1629-34, Aug.-Oct. 2000.
• 32: TI Wire planning for performance and yield enhancement. AU Ouyang-C; Ryu-K; Heineken-H; Khare-J; Shaikh-S; d-Abreu-M. SO Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, Orlando, FL, USA, 21-24 May 2000. In: p.113-16, 2000.
• 33: Israel Koren , Zahava Koren, Incorporating Yield Enhancement into the Floorplanning Process, IEEE Transactions on Computers, v.49 n.6, p.532-541, June 2000 [doi>10.1109/12.862213]
• 34: Youcef Bourai , C.-J. Richard Shi, Layout compaction for yield optimization via critical area minimization, Proceedings of the conference on Design, automation and test in Europe, p.122-127, March 27-30, 2000, Paris, France [doi>10.1145/343647.343717]
• 35: Witold A. Pleskacz, Yield Estimation of VLSI Circuits with Downscaled Layouts, Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.55-60, November 01-03, 1999
• 36: Arunshankar Venkataraman , Israel Koren, Determination of Yield Bounds Prior to Routing, Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.4-13, November 01-03, 1999
• 37: Israel Koren , Zahava Koren, Yield and Routing Objectives in Floorplanning, Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.28-36, November 02-04, 1998
• 38: Jeffrey Z. Su , Wayne W. Dai, Post-route optimization for improved yield using a rubber-band wiring model, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.700-706, November 09-13, 1997, San Jose, California, United States
• 39: A. J. Strojwas, Design for manufacturability and yield, Proceedings of the 26th ACM/IEEE conference on Design automation, p.454-459, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74458]
• 40: TI Integrated circuit yield management and yield analysis: development and implementation. AU Stapper-C-H; Rosner-R-J. SO IEEE-Transactions-on-Semiconductor-Manufacturing (USA), vol.8, no.2, p.95-102, May 1995.
• 41: TI Yield models-comparative study. AU Maly-W; Ed. by Stapper-C-H; Jain-V-K; Saucier-G. SO Defect and Fault Tolerance in VLSI Systems. Vol.2. Proceedings of the International Workshop, Tampa, FL, USA, 22- 24 Oct. 1989, p.15-32. Published: Plenum, New York, NY, USA, 1990, x+316 pp.
• 42: TI Fact and fiction in yield modeling. AU Stapper-C-H. SO 17th Yugoslav Conference on Microelectronics. Proceedings, Nis, Yugoslavia, 9-11 May 1989, p.52-94 vol.1. Published: Elsevier Adv. Technol, Oxford, UK, 1989, 2 vol. 982 pp.
• 43: C. H. Stapper, Small-area fault clusters and fault tolerance in VLSI circuits, IBM Journal of Research and Development, v.33 n.2, p.174-177, March 1989
• 44: C. H. Stapper, Large-area fault clusters and fault tolerance in VLSI circuits, IBM Journal of Research and Development, v.33 n.2, p.162-173, March 1989
• 45: TI Fact and fiction in yield modeling (ICs). AU Stapper-C-H. SO Microelectronics-Journal (UK), vol.20, no.1-2, p.129-51, Spring 1989.
• 46: TI Yield statistics for large area ICs. AU Stapper-C-H; Ed. by Winner-L. SO 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Anaheim, CA, USA, 19-21 Feb.1986, p.168-9.
• 47: C H Stapper, On yield, fault distributions, and clustering of particles, IBM Journal of Research and Development, v.30 n.3, p.326-338, May 1986
• 48: Charles H. Stapper, Yield model for fault clusters within integrated circuits, IBM Journal of Research and Development, v.28 n.5, p.636-640, September 1984
• 49: TI Modeling of defects in integrated circuit photolithographic patterns AU Stapper-C-H. SO IBM-Journal-of-Research-and-Development (USA), vol.28, no.4, p.461-74, July 1984.
• 50: TI Integrated circuit yield statistics. AU Stapper-C-H; Armstrong-F-M; Saji-K. SO Proceedings-of-the-IEEE (USA), vol.71, no.4, p.453-70, April 1983.
• 51: TI Modeling of integrated circuit defect sensitivities (for LSI). AU Stapper-C-H. SO IBM-Journal-of-Research-and-Development (USA), vol.27, no.6, p.549-57, Nov. 1983.
• 52: TI Yield estimation model for VLSI artwork evaluation. AU Maly-W; Deszczka-J. SO Electronics-Letters (UK), vol.19, no.6, p.226-7, 17 March 1983.
• 53: TI IC defect sensitivity for footprint-type spot defects. AU Pineda-de-Gyvez-J; Di-C. SO IEEE-Transactions-on-Computer-Aided-Design-of-Integrated-Circuits-and-Systems (USA), vol.11, no.5, p.638-58, May 1992.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization

  J. Computer Applications
  J.1 ADMINISTRATIVE DATA PROCESSING
      Subjects: Manufacturing
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Algorithms, Design, Management, Performance, Theory