Importance of CAD tools and methodology in high speed CPU design

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Importance of CAD tools and methodology in high speed CPU design: invited talk

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 631 - 634

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Haruyuki Tago	System ULSI Engineering Lab., Toshiba Corporation, Semicondoctor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan 212-8520
Kazuhiro Hashimoto	System ULSI Engineering Lab., Toshiba Corporation, Semicondoctor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan 212-8520
Nobuyuki Ikumi	System ULSI Engineering Lab., Toshiba Corporation, Semicondoctor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan 212-8520
Masato Nagamatsu	System LSI Design Division, Toshiba Corporation, Semicondoctor Company, 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, Japan 212-8520
Masakazu Suzuoki	R&D Division, Sony Computer Entertainment Inc., 1-1, Akasaka 7-chome, Minato-ku, Tokyo, Japan 107-0052
Yasuyuki Yamamoto	R&D Division, Sony Computer Entertainment Inc., 1-1, Akasaka 7-chome, Minato-ku, Tokyo, Japan 107-0052

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 8, Citation Count: 2

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references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Ken Kutaragi, et al., "A Microprocessor with a 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.256-257, 1999.
	2	F. Michael Raam, et al., "A High Bandwidth Superscalar Microprocessor for Multimedia Applications," IEEE ISSCC Digest of Technical Papers, Vol.42, pp.258-259, 1999.
	3	Takayuki Kamei , Hideaki Takeda , Yukio Ootaguro , Takayoshi Shimazawa , Kazuhiko Tachibana , Shin'ichi Kawakami , Seiji Norimatsu , Fujio Ishihara , Toshinori Sato , Hiroaki Murakami , Nobuhiro Ide , Yukio Endo , Akira Aono , Atsushi Kunimatsu, 300MHz design methodology of VU for emotion synthesis, Proceedings of the 2000 conference on Asia South Pacific design automation, p.635-640, January 2000, Yokohama, Japan [doi>10.1145/368434.368847]
	4	Norman Kojima , Yukiko Parameswar , Christian Klingner , Yukio Ohtaguro , Masataka Matsui , Shigeaki Iwasa , Tatsuo Teruyama , Takayoshi Shimazawa , Hideki Takeda , Kouji Hashizume , Haruyuki Tago , Masaaki Yamada, Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor, Proceedings of the 2000 conference on Asia South Pacific design automation, p.641-646, January 2000, Yokohama, Japan [doi>10.1145/368434.368852]
	5	Fujio Ishihara , Christian Klinger , Ken-ichi Agawa, Clock design of 300MHz 128-bit 2-way superscalar microprocessor, Proceedings of the 2000 conference on Asia South Pacific design automation, p.647-652, January 2000, Yokohama, Japan [doi>10.1145/368434.368857]

CITED BY 2

	Atsushi Kunimatsu , Nobuhiro Ide , Toshinori Sato , Yukio Endo , Hiroaki Murakami , Takayuki Kamei , Masashi Hirano , Fujio Ishihara , Haruyuki Tago , Masaaki Oka , Akio Ohba , Teiji Yutaka , Toyoshi Okada , Masakazu Suzuoki, Vector Unit Architecture for Emotion Synthesis, IEEE Micro, v.20 n.2, p.40-47, March 2000
	Kaijian Shi , Graig Godwin, Hybrid hierarchical timing closure methodology for a high performance and low power DSP, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA

Collaborative Colleagues:

Haruyuki Tago: colleagues

Kazuhiro Hashimoto: colleagues

Nobuyuki Ikumi: colleagues

Masato Nagamatsu: colleagues

Masakazu Suzuoki: colleagues

Yasuyuki Yamamoto: colleagues

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