Performance sensitivity analysis using statistical method and its applications to delay

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Performance sensitivity analysis using statistical method and its applications to delay

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 587 - 592

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Jing-Jia Liou	ECE Department, University of California, Santa Barbara and Intel Corporation
Angela Krstic	ECE Department, University of California, Santa Barbara and Intel Corporation
Kwang-Ting Cheng	ECE Department, University of California, Santa Barbara and Intel Corporation
Deb Aditya Mukherjee	ECE Department, University of California, Santa Barbara and Intel Corporation
Sandip Kundu	ECE Department, University of California, Santa Barbara and Intel Corporation

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 21, Citation Count: 13

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anacad. Eldo v4.4.x User's Manual, 1996.
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	3	M. A. Breuer, C. Gleason, and S. Gupta. New Validation and Test Problems for High Performance Deep Sub-Micron VLSI Circuits. VTS, Tutorial Notes, Apr. 1997.
	4	Kwang-Ting Cheng , Angela Krstic , Hsi-Chuan Chen, Generation of High Quality Tests for Robustly Untestable Path Delay Faults, IEEE Transactions on Computers, v.45 n.12, p.1379-1392, December 1996 [doi>10.1109/12.545968]
	5	H. Edamatsu, K. Homma, M. Kakimoto, Y. Koike, and K. Tabuchi. Pre-Layout Delay Calculation Specification for CMOS ASIC Libraries. Proc. of ASP-DAC, pp. 241-248, Feb. 1998.
	6	Horng-Fei Jyu , Sharad Malik, Statistical delay modeling in logic design and synthesis, Proceedings of the 31st annual conference on Design automation, p.126-130, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196304]
	7	H.-F. Jyu, S. Malik, S. Devadas, and K. Keutzer. Statistical Timing Analysis of Combinational Logic Circuits. IEEE Trans. on VLSI Systems, 1(2):126-137, June 1993.
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	9	J. Power, B. Donnellan, A. Mathewson, and W. Lane. Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design. IEEE Trans. on Semiconductor Manufacturing, 7(3):306-318, Aug. 1994.
	10	J. Qian, S. Pullela, and L. Pillage. Modeling The "Effective Capacitance" for The RC Interconnect of CMOS Gates. IEEE Trans. on CAD, 13(12):1526-1535, Dec. 1994.
	11	C. L. Ratzlaff and L. T. Pillage. RICE: Rapid Interconnect Circuit Evaluation Using AWE. IEEE Trans. on CAD, 13(6):763-776, June 1994.
	12	Fred M. Armstrong , Mark R. Reiter , David R. Tryon, Statistical failure analysis of system timing, IBM Journal of Research and Development, v.28 n.4, p.340-355, July 1984

CITED BY 13

	Jing-Jia Liou , Li-C. Wang , Kwang-Ting Cheng , Jennifer Dworak , M. Ray Mercer , Rohit Kapur , Thomas W. Williams, Enhancing test efficiency for delay fault testing using multiple-clocked schemes, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States
	Jing-Jia Liou , Angela Krstic , Li-C. Wang , Kwang-Ting Cheng, False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jing-Jia Liou , Li-C. Wang , Angela Krstic , Kwang-Ting Cheng, Experience in critical path selection for deep sub-micron delay test and timing validation, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	A. Krstic , L.-C. Wang , K.-T. Cheng , J.-J. Liou , T. M. Mak, Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Li-C. Wang , T. M. Mak , Kwang-Ting Cheng , Magdy S. Abadir, On path-based learning and its applications in delay test and diagnosis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Kai Yang , Kwang-Ting Cheng , Li-C. Wang, TranGen: a SAT-based ATPG for path-oriented transition faults, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.92-97, January 27-30, 2004, Yokohama, Japan
	Jing Jia Liou , Angela Krstić , Yi Min Jiang , Kwang Ting Cheng, Path selection and pattern generation for dynamic timing analysis considering power supply noise effects, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Bipul C. Paul , Kaushik Roy, Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits, Journal of Electronic Testing: Theory and Applications, v.22 n.2, p.115-124, April 2006
	L. Lee , Li-C Wang , T. M. Mak , Kwang-Ting Cheng, A path-based methodology for post-silicon timing validation, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.713-720, November 07-11, 2004
	Angela Krstic , Li-C. Wang , Kwang-Ting Cheng , Jing-Jia Liou , Magdy S. Abadir, Delay Defect Diagnosis Based Upon Statistical Timing Models " The First Step, Proceedings of the conference on Design, Automation and Test in Europe, p.10328, March 03-07, 2003
	Li-C. Wang, Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation, Proceedings of the conference on Design, automation and test in Europe, p.10692, February 16-20, 2004
	Ying-Yen Chen , Jing-Jia Liou, Diagnosis framework for locating failed segments of path delay faults, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.755-765, June 2008

Collaborative Colleagues:

Jing-Jia Liou: colleagues

Angela Krstic: colleagues

Kwang-Ting Cheng: colleagues

Deb Aditya Mukherjee: colleagues

Sandip Kundu: colleagues

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