| Retargetable estimation scheme for DSP architecture selection |
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Asia and South Pacific Design Automation Conference
archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
Pages: 485 - 490
Year of Publication: 2000
ISBN:0-7803-5974-7
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Authors
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Naji Ghazal
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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Richard Newton
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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Jan Rabaey
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Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 4
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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Silvina Hanono , Srinivas Devadas, Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator, Proceedings of the 35th annual conference on Design automation, p.510-515, June 15-19, 1998, San Francisco, California, United States
[doi> 10.1145/277044.277184]
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V. Zivojnovic , S. Pees , C. Schlager , M. Willems , R. Schoenen , H. Meyr, DSP processor/compiler co-design: a quantitative approach, Proceedings of the 9th international symposium on System synthesis, p.108, November 06-08, 1996
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Bier, J. "Processors for DSP--the options multiply," The Embedded Processor Forum. MicroDesign Resources, 1998.
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Bier, J., et. al., Evaluating DSP processor performance," white paper, Berkeley Design Technologies Inc. (BDTI), 1996.
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M. Yamguchi, et. al., "Architecture evaluation based on datapath structure and parallel constraint." Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 503-08, January 1997.
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George Hadjiyiannis , Silvina Hanono , Srinivas Devadas, ISDL: an instruction set description language for retargetability, Proceedings of the 34th annual conference on Design automation, p.299-302, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266108]
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V. Zivojnovic, S. Pees, and H. Meyr, "LISA-machine description language and generic machine model for HW/SW co-design." VLSI Signal Processing, IX, pp. 127-36, 1996.
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LSI Logic Corporation (formerly ZSP), "LSI401Z DSP," technical note. http://www.zsp.com/pdf/LSI401.pdf, 1998
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Stanford Compiler Group. The SUIF Library, version 1.0, http://suif.stanford.edu. 1994
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B. Rau, "Iterative modulo scheduling." International Journal of Parallel Programming, vol.24, pp.3-64, Feb. 1996.
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LSI Logic Corporation (formerly ZSP Corporation), The ZSP164xx Programmer's Reference Manual. 1997.
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Texas Instruements. TMS320C6000 CPU and instruction set reference guide http://www.ti.com/sc/psheets/spru189d/spru189d.pdf, 1997.
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CITED BY 4
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Naji Ghazal , Richard Newton , Jan Rabaey, Predicting performance potential of modern DSPs, Proceedings of the 37th conference on Design automation, p.332-335, June 05-09, 2000, Los Angeles, California, United States
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Manoj Kumar Jain , Lars Wehmeyer , Stefan Steinke , Peter Marwedel , M. Balakrishnan, Evaluating register file size in ASIP design, Proceedings of the ninth international symposium on Hardware/software codesign, p.109-114, April 2001, Copenhagen, Denmark
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Manoj Kumar Jain , M. Balakrishnan , Anshul Kumar, An efficient technique for exploring register file size in ASIP synthesis, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
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