Optimization of VDD and VTH for low-power and high speed applications

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Optimization of VDD and VTH for low-power and high speed applications

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 469 - 474

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Koichi Nose	Institute of Industrial Science, University of Tokyo, 7-22-1 Roppongi, Minato-ku, Tokyo, 106-8558 Japan
Takayasu Sakurai	Institute of Industrial Science, University of Tokyo, 7-22-1 Roppongi, Minato-ku, Tokyo, 106-8558 Japan

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 100, Citation Count: 18

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Burr and A. Perterson, "Ultra low power CMOS technology, " NASA VLSI Design Symposium, pp. 4.2.1-4.2.13, 1991.
	2	R. Gonzalez, B. M. Gordon and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS, " IEEE Jounal of Solid-State Circuit, vol. 32, pp. 1210-1216, Aug., 1997.
	3	Z. Chen, C. Diaz, J. D. Plummer, M.Cao and W. Greene, "0.18um dual Vt MOSFET processing and energy-delay measurement," IEDM tech. digest, pp. 851-854, 1996.
	4	The National Technology Roadmap for Semiconductors, SIA Handbook, 1998.
	5	K. Nose and T. Sakurai, "Closed-Form Expressions for Short-Circuit Power of Short-Channel CMOS Gates and Its Scaling Characteristics," Proceedings of ITC-CSCC, pp.1741-1744, July, 1998.
	6	T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas," IEEE Jounal of Solid-State Circuits, vol.25, pp. 584-593, Apr., 1990.
	7	A. Bellaouar, A. Fridi, M. I. Elmasry and K. Itoh, "Supply voltage scaling for temperature insensitive CMOS circuit operation," IEEE Transaction on Circuit and Systems II, vol. 45, pp. 415 -417, Mar., 1998.
	8	C. Park et al, "Reversal of temperature dependence of integrated circuits operation at very low voltages," IEDM Tech., Digest, pp. 71-74, 1995.
	9	K. Kanda, K. Nose, H. Kawaguchi and T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub IV CMOS VLSI's," Proceedings CICC'99, pp.563-566, May, 1999.
	10	Yuan Taur , Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, New York, NY, 1998
	11	J. Burr and J. Shott, "A 200mV encoder-decoder circuit using Stanford Ultra Low -Power CMOS," ISSCC Digest of Tech. Papers, pp. 84-85, Feb., 1994.
	12	H.Kawaguchi, Y.Itaka and T.Sakurai, "Dynamic Leakage Cut-off Scheme for Low-Voltage SRAM's," Symp. on VLSI Circuits, pp.140-141, June, 1998.

CITED BY 18

	Masayuki Hirabayashi , Koichi Nose , Takayasu Sakurai, Design methodology and optimization strategy for dual-VTH scheme using commercially available tools, Proceedings of the 2001 international symposium on Low power electronics and design, p.283-286, August 2001, Huntington Beach, California, United States
	Koichi Nose , Soo-Ik Chae , Takayasu Sakurai, Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.228-230, July 25-27, 2000, Rapallo, Italy
	Yann-Hang Lee , Yoonmee Doh , C. M. Krishna, EDF scheduling using two-mode voltage-clock-scaling for hard real-time systems, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
	Mongkol Ekpanyapong , Sung Kyu Lim, Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Takayasu Sakurai, Minimizing power across multiple technology and design levels, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.24-27, November 10-14, 2002, San Jose, California
	Ashish Srivastava , Dennis Sylvester, Minimizing total power by simultaneous Vdd/Vth assignment, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Anirban Basu , Sheng-Chih Lin , Vineet Wason , Amit Mehrotra , Kaustav Banerjee, Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Dongwoo Lee , David Blaauw , Dennis Sylvester, Gate oxide leakage current analysis and reduction for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.155-166, February 2004
	Benton H. Calhoun , Anantha Chandrakasan, Characterizing and modeling minimum energy operation for subthreshold circuits, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Tadahiro Kuroda, Optimization and control of V_DD and V_TH for low-power, high-speed CMOS design, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.28-34, November 10-14, 2002, San Jose, California
	Ja Chun Ku , Yehea Ismail, Area optimization for leakage reduction and thermal stability in nanometer scale technologies, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Robert W. Brodersen , Mark A. Horowitz , Dejan Markovic , Borivoje Nikolic , Vladimir Stojanovic, Methods for true power minimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.35-42, November 10-14, 2002, San Jose, California
	Schuster Christian , Nagel Jean-Luc , Piguet Christian , Farine Pierre-André, Architectural and technology influence on the optimal total power consumption, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Joonsoo Kim , Michael Orshansky, Towards formal probabilistic power-performance design space exploration, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Yuvraj Singh Dhillon , Abdulkadir Utku Diril , Abhijit Chatterjee , Hsien-Hsin Sean Lee, Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.693, November 09-13, 2003
	Jie Zhang , Nishant P. Patil , Subhasish Mitra, Design guidelines for metallic-carbon-nanotube-tolerant digital logic circuits, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	Shuo Wang , Jianwei Dai , El-Sayed Hasaneen , Lei Wang , Faquir Jain, Utilizing quantum dot transistors with programmable threshold voltages for low-power mobile computing, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.5 n.3, p.1-19, August 2009

Collaborative Colleagues:

Koichi Nose: colleagues

Takayasu Sakurai: colleagues

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