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IBAW: an implication-tree based alternative-wiring logic transformation algorithm

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 415 - 422

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Wangning Long	Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, China
Yu-Liang Wu	Dept. Computer Sci. & Eng., The Chinese University of HK, Shatin, NT, Hong kong
Jinian Bian	Dept. Computer Sci. & Tech., Tsinghua University, Beijing, 100084, China

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 6, Citation Count: 3

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E M Sentovich, K J Singh, L Lavagno, et. al., "SIS: A System for Sequential Circuit Synthesis", ERL Memorandum No. UCB/ERL M92/41, 1992.
	2	Chih Wei Jim Chang , Malgorzata Marek-Sadowska, Single-pass redundancy addition and removal, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	3	L A Entrena and K-T Cheng, "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal", IEEE Trans CAD of ICAS, Vol. 14, No. 7, July, 1995, pp. 909 - 916.
	4	Wolfgang Kunz , Prem R. Menon, Multi-level logic optimization by implication analysis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.6-13, November 06-10, 1994, San Jose, California, United States
	5	M Chatterjee, D K Pradhan, and W Kunz, "LOT: Logic Optimization with Testability- New Transformations for Logic Synthesis", IEEE Trans CAD of ICAS, Vol. 17, No 5, May 1998, pp. 386 - 399.
	6	S-C Chang, M Marek-Sadowska, and K-T Cheng, "Perturb and Simplify: Multilevel Boolean Network Optimizer", IEEE Trans CAD ofICAS, Vol. 15, No. 12, Dec 1996, pp. 1494 - 1504.
	7	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	8	H Ichihara, K Kinoshita. "Logic Optimization: Redundancy Addition and Removal Using Implication Relationships", IEICE Trans Inf. & Syst, E8 l-D(7), 1998, pp. 724- 730.
	9	H Fujiwara, and T Shimono, "On the Acceleration of Test Generation Algorithms", in Proc of 13th International Symposium on Fault Tolerant Computing, 1983, pp. 98 - 105.
	10	Wolfgang Kunz , Dhiraj K. Pradhan, Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.816-825, September 20-24, 1992
	11	S-C Chang, K-T Cheng, N-S Woo, and M Marek- Sadowska, "Postlayout Logic Restructuring Using Alternative Wires", IEEE Trans CAD of ICAS, Vol. 16, No. 6, June 1997, pp. 587- 596.
	12	Yi-Min Jiang , Angela Krstic , Kwang-Ting Cheng , Malgorzata Marek-Sadowska, Post-layout logic restructuring for performance optimization, Proceedings of the 34th annual conference on Design automation, p.662-665, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266313]
	13	David Ihsin Cheng , Chih-Chang Lin , Malgorzata Marek-Sadowska, Circuit partitioning with logic perturbation, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.650-655, November 05-09, 1995, San Jose, California, United States
	14	W Long, "Study on Alternative Wiring Logic Synthesis System", Post-doctoral Research Report, Tsinghua University, Beijing, China, 1999.

CITED BY 3

	Chin-Ngai Sze , Yu-Liang Wu, Improved alternative wiring scheme applying dominator relationship, Proceedings of the 2001 conference on Asia South Pacific design automation, p.473-478, January 2001, Yokohama, Japan
	Alexey Glebov , Sergey Gavrilov , David Blaauw , Supamas Sirichotiyakul , Chanhee Oh , Vladimir Zolotov, False-noise analysis using logic implications, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	False-noise analysis using logic implications, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.7 n.3, p.474-498, July 2002

Collaborative Colleagues:

Wangning Long: colleagues

Yu-Liang Wu: colleagues

Jinian Bian: colleagues

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