Narrow bus encoding for low power systems

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Narrow bus encoding for low power systems

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 217 - 220

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Youngsoo Shin	School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea
Kiyoung Choi	School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 17, Citation Count: 5

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	O. Gunasekara, "Developing a digital cellular phone using a 32-bit microcontroller," Tech. Rep., Advanced RISC Machines Ltd., 1998.
	2	D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 663-670, June 1994.
	3	C. L. Su, C. Y. Tsui, and A. M. Despain, "Low power architecture design and compilation technique for high-performance processors," in Proc. IEEE COMPCON, Feb. 1994, pp. 209-214.
	4	M. R. Stan and W. P. Burleson, "Limited-weight codes for low-power I/O," in Proc. Int'l Workshop on Low Power Design, Apr. 1994, pp. 209-214.
	5	Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
	6	Mircea R. Stan , Wayne P. Burleson, Low-power encodings for global communication in CMOS VLSI, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.444-455, Dec. 1997 [doi>10.1109/92.645071]
	7	Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
	8	Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Stefano Quer, System-level power optimization of special purpose applications: the beach solution, Proceedings of the 1997 international symposium on Low power electronics and design, p.24-29, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263277]
	9	Youngsoo Shin , Soo-IK Chae , Kiyoung Choi, Partial bus-invert coding for power optimization of system level bus, Proceedings of the 1998 international symposium on Low power electronics and design, p.127-129, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280829]
	10	R. J. Fletcher, "Integrated circuit having outputs configured for reduced state changes," May 1987, U.S. Patent 4667337.
	11	Paul E. Landman , Jan M. Rabaey, Architectural power analysis: the dual bit type method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.2, p.173-187, June 1995 [doi>10.1109/92.386219]
	12	J. M. Rabaey , C. Chu , P. Hoang , M. Potkonjak, Fast Prototyping of Datapath-Intensive Architectures, IEEE Design & Test, v.8 n.2, p.40-51, April 1991 [doi>10.1109/54.82037]
	13	S. Lee and W. Sung, "A parser processor for MPEG-2 audio and AC-3 decoding," in Proc. Int'l Symposium on Circuits and Systems, June 1997, pp. 2621-2624.

CITED BY 5

	Youngsoo Shin , Takayasu Sakurai, Coupling-driven bus design for low-power application-specific systems, Proceedings of the 38th conference on Design automation, p.750-753, June 2001, Las Vegas, Nevada, United States
	Massoud Pedram, Power optimization and management in embedded systems, Proceedings of the 2001 conference on Asia South Pacific design automation, p.239-244, January 2001, Yokohama, Japan
	K. Basu , A. Choudhary , J. Pisharath , M. Kandemir, Power protocol: reducing power dissipation on off-chip data buses, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Hidehiro Fujiwara , Koji Nii , Junichi Miyakoshi , Yuichiro Murachi , Yasuhiro Morita , Hiroshi Kawaguchi , Masahiko Yoshimoto, A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Hidehiro Fujiwara , Koji Nii , Hiroki Noguchi , Junichi Miyakoshi , Yuichiro Murachi , Yasuhiro Morita , Hiroshi Kawaguchi , Masahiko Yoshimoto, Novel video memory reduces 45% of bitline power using majority logic and data-bit reordering, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.6, p.620-627, June 2008

Collaborative Colleagues:

Youngsoo Shin: colleagues

Kiyoung Choi: colleagues

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