Taiwan foundry for system-in-package (SIP)

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Taiwan foundry for system-in-package (SIP)

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 197 - 204

Year of Publication: 2000

ISBN:0-7803-5974-7

Author

Albert Lin

APack Technologies Inc., Hsinchu, Taiwan, ROC

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 14, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. D. Dudderar, Y. Degani, J. G. Spadafora and K. L. Tai "AT&T m-Surface Mount Assembly: A New Technology for the Large Volume Fabrication of Cost Effective Flip-chip MCMs," Proceedings of International Conference Multichip Modules, p. 266, Denver, CO, April 13-15 (1994).
	2	K. L. Tai, R. C. Frye, B. J. Han, M. Y. Lau and D. P. Kossives, "A Chip-on-Chip DSP/SRAM multichip Module," Proc. 1995 Int'l Conf. On Multichip Modules Denver, CO, April 19-21 (1995).
	3	Y. L. Low, R. C. Frye and K. J. O'Connor, "Design Methodology for Chip-on-Chip Applications," IEEE Transactions on Components, Packaging and Manufacturing Technology-Part B, Vol. 21, No.3, August (1998).
	4	Y. L. Low and K. J. O'Connor, "Electrical Performance of Chip-on-Chip Modules," IEEE 7 th Topic Meeting on Electrical Performance of Electronic Packaging, October 26-28 (1998).
	5	K. J. O'Connor , Y. L. Low , J. A. Gregus , Y. Degani, Memory Performance in Chip-On-Chip Packages: Optimizing Memory/ASIC Integration, Proceedings of the IEEE Symposium on IC/Package Design Integration, p.16, February 02-03, 1998
	6	J. A. Gregus, M. Y. Lau, Y. Degani and K. L. Tai, "Chip Scale Modules for High Level Integration in the 21 st Century," Bell Labs Technical Journal, p.116-124, July-September (1998).

Collaborative Colleagues:

Albert Lin: colleagues

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