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Analytical minimization of half-perimeter wirelength
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 179 - 184  
Year of Publication: 2000
ISBN:0-7803-5974-7
Authors
Andrew A. Kennings  Dept. Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L 3G1 and UCLA Computer Science, Los Angeles, CA
Igor L. Markov  Dept. Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L 3G1 and UCLA Computer Science, Los Angeles, CA
Sponsors
IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 20,   Citation Count: 9
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references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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C. J. Alpert, A. E. Caldwell, T. Chan, D. J.-H. Huang, A. B. Kahng, I. L. Markov and M. Moroz, "Analytical Engines Are Unnecessary in Top-down Partitioning-Based Placement" VLSI Design (1999), to appear.
 
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R. Baldick, A. Kahng, A. Kennings and I. Markov, "Function Smoothing with Applications to VLSI Layout", Proc. ASP-DAC '99, pp. 225-228.
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R. Fletcher and M.J.D. Powell, "A Rapidly Convergent Descent Method for Minimization", Computer J. 6, 1963, pp. 163-168.
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M. Hanan, P. K.Wolff, and B. J. Agule, "A Study of Placement Techniques." J. Design Automation and Fault-Tolerant Computing, vol. 2, 1978, pp. 28-61.
 
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T. Koide at al, "Par-POPINS: a Timing-driven Parallel Placement Method With the Elmore Delay Model For Row Based VLSIs", Proc. ASP-DAC '97, 1997. pp. 133-40.
 
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I. I. Mahmoud, K. Asakura, T. Nishibu and T. Ohtsuki, "Experimental Appraisal of Linear and Quadratic Objective Functions Effect on Force Directed Method for Analog Placement", IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences 4(E77-A), 1994, pp. 710-725.
 
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J. Nocedal, "Large Scale Unconstrained Optimization", The State of the Art in Numerical Analysis, Ed. A Watson and I. Duff, Oxford University Press, 1996.
 
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B. M. Riess and G. G. Ettelt, "Speed: Fast and Efficient Timing Driven Placement", Proc. ISCAS '95, pp. 377-380.
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A. Srinivasan, K. Chaudhary and E. S. Kuh, "RITUAL: A Performance Driven Placement for Small-Cell ICs", Proc. ICCAD '91, pp. 48-51.
 
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Takahashi, K.; Nakajima, K.; Terai, M.; Sato, K., "Min-cut Placement With Global Objective Functions For Large Scale Sea-of-gates Arrays.", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 4, April 1995, pp. 434-446.
 
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R. S. Tsay, E. Kuh, "A Unified Approach to Partitioning and Placement", IEEE Transactions on Circuits and Systems, Vol.38, No.5, May 1991. pp., 521-633.
 
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Y.-W. Tsay, H.-P. Su, Y.-L. Lin, "An Improved Objective For Cell Placement", Proc. ASP-DAC '97, Japan, 1997, pp. 281- 284.
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J. Vygen, Personal Communication, November, 1999.
 
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B. X. Weis and D. A. Mlynski, "A New Relative Placement Procedure Based on MSST and Linear Programming. Proc. ISCAS '87, pp. 564-567.

CITED BY  9
Collaborative Colleagues:
Andrew A. Kennings: colleagues
Igor L. Markov: colleagues